1 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
4 ; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 13
5 define void @v1(i32 %a1) #0 {
7 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
8 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
9 %2 = extractelement <4 x float> %1, i32 0
10 %3 = extractelement <4 x float> %1, i32 2
11 %4 = extractelement <4 x float> %1, i32 3
12 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
17 ; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 11
18 define void @v2(i32 %a1) #0 {
20 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
21 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
22 %2 = extractelement <4 x float> %1, i32 0
23 %3 = extractelement <4 x float> %1, i32 1
24 %4 = extractelement <4 x float> %1, i32 3
25 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
30 ; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 14
31 define void @v3(i32 %a1) #0 {
33 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
34 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
35 %2 = extractelement <4 x float> %1, i32 1
36 %3 = extractelement <4 x float> %1, i32 2
37 %4 = extractelement <4 x float> %1, i32 3
38 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
43 ; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 7
44 define void @v4(i32 %a1) #0 {
46 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
47 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
48 %2 = extractelement <4 x float> %1, i32 0
49 %3 = extractelement <4 x float> %1, i32 1
50 %4 = extractelement <4 x float> %1, i32 2
51 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
56 ; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 10
57 define void @v5(i32 %a1) #0 {
59 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
60 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
61 %2 = extractelement <4 x float> %1, i32 1
62 %3 = extractelement <4 x float> %1, i32 3
63 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
68 ; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 6
69 define void @v6(i32 %a1) #0 {
71 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
72 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
73 %2 = extractelement <4 x float> %1, i32 1
74 %3 = extractelement <4 x float> %1, i32 2
75 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
80 ; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 9
81 define void @v7(i32 %a1) #0 {
83 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
84 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
85 %2 = extractelement <4 x float> %1, i32 0
86 %3 = extractelement <4 x float> %1, i32 3
87 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
91 declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone
93 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
95 attributes #0 = { "ShaderType"="0" }