1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
2 ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
4 @local_memory_two_objects.local_mem0 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4
5 @local_memory_two_objects.local_mem1 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4
7 ; EG-CHECK: @local_memory_two_objects
9 ; Check that the LDS size emitted correctly
10 ; EG-CHECK: .long 166120
11 ; EG-CHECK-NEXT: .long 8
12 ; SI-CHECK: .long 47180
13 ; SI-CHECK-NEXT: .long 32768
15 ; We would like to check the the lds writes are using different
16 ; addresses, but due to variations in the scheduler, we can't do
17 ; this consistently on evergreen GPUs.
20 ; SI-CHECK: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
21 ; SI-CHECK-NOT: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW]]
23 ; GROUP_BARRIER must be the last instruction in a clause
24 ; EG-CHECK: GROUP_BARRIER
25 ; EG-CHECK-NEXT: ALU clause
27 ; Make sure the lds reads are using different addresses.
28 ; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
29 ; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
30 ; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]]
31 ; SI-CHECK-NOT: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]]
33 define void @local_memory_two_objects(i32 addrspace(1)* %out) {
35 %x.i = call i32 @llvm.r600.read.tidig.x() #0
36 %arrayidx = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
37 store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
38 %mul = shl nsw i32 %x.i, 1
39 %arrayidx1 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
40 store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
41 %sub = sub nsw i32 3, %x.i
42 call void @llvm.AMDGPU.barrier.local()
43 %arrayidx2 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
44 %0 = load i32 addrspace(3)* %arrayidx2, align 4
45 %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %x.i
46 store i32 %0, i32 addrspace(1)* %arrayidx3, align 4
47 %arrayidx4 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
48 %1 = load i32 addrspace(3)* %arrayidx4, align 4
49 %add = add nsw i32 %x.i, 4
50 %arrayidx5 = getelementptr inbounds i32 addrspace(1)* %out, i32 %add
51 store i32 %1, i32 addrspace(1)* %arrayidx5, align 4
55 declare i32 @llvm.r600.read.tidig.x() #0
56 declare void @llvm.AMDGPU.barrier.local()
58 attributes #0 = { readnone }