1 ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
3 ; In this test both the pointer and the offset operands to the
4 ; BUFFER_LOAD instructions end up being stored in vgprs. This
5 ; requires us to add the pointer and offset together, store the
6 ; result in the offset operand (vaddr), and then store 0 in an
7 ; sgpr register pair and use that for the pointer operand
8 ; (low 64-bits of srsrc).
12 ; Make sure we aren't using VGPRs for the source operand of S_MOV_B64
13 ; CHECK-NOT: S_MOV_B64 s[{{[0-9]+:[0-9]+}}], v
15 ; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
17 ; CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}]
18 ; CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}]
19 define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
21 %0 = call i32 @llvm.r600.read.tidig.x() #1
22 %1 = call i32 @llvm.r600.read.tidig.y() #1
23 %2 = sext i32 %0 to i64
24 %3 = sext i32 %1 to i64
28 %4 = phi i64 [0, %entry], [%5, %loop]
30 %6 = getelementptr i8 addrspace(1)* %in, i64 %5
31 %7 = load i8 addrspace(1)* %6, align 1
33 %9 = getelementptr i8 addrspace(1)* %in, i64 %8
34 %10 = load i8 addrspace(1)* %9, align 1
36 %12 = sext i8 %11 to i32
37 store i32 %12, i32 addrspace(1)* %out
38 %13 = icmp slt i64 %5, 10
39 br i1 %13, label %loop, label %done
45 declare i32 @llvm.r600.read.tidig.x() #1
46 declare i32 @llvm.r600.read.tidig.y() #1
48 attributes #1 = { nounwind readnone }