1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4 declare i32 @llvm.AMDGPU.imax(i32, i32) nounwind readnone
7 ; FUNC-LABEL: @sext_in_reg_i1_i32
8 ; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
9 ; SI: S_BFE_I32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000
10 ; SI: V_MOV_B32_e32 [[EXTRACT:v[0-9]+]], [[SEXTRACT]]
11 ; SI: BUFFER_STORE_DWORD [[EXTRACT]],
13 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
14 ; EG: BFE_INT [[RES]], {{.*}}, 0.0, 1
15 ; EG-NEXT: LSHR * [[ADDR]]
16 define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) {
17 %shl = shl i32 %in, 31
18 %sext = ashr i32 %shl, 31
19 store i32 %sext, i32 addrspace(1)* %out
23 ; FUNC-LABEL: @sext_in_reg_i8_to_i32
24 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
25 ; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
26 ; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
27 ; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
29 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
31 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
32 ; EG-NEXT: LSHR * [[ADDR]]
33 define void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
34 %c = add i32 %a, %b ; add to prevent folding into extload
36 %ashr = ashr i32 %shl, 24
37 store i32 %ashr, i32 addrspace(1)* %out, align 4
41 ; FUNC-LABEL: @sext_in_reg_i16_to_i32
42 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
43 ; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]]
44 ; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
45 ; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
47 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
49 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
50 ; EG-NEXT: LSHR * [[ADDR]]
51 define void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
52 %c = add i32 %a, %b ; add to prevent folding into extload
54 %ashr = ashr i32 %shl, 16
55 store i32 %ashr, i32 addrspace(1)* %out, align 4
59 ; FUNC-LABEL: @sext_in_reg_i8_to_v1i32
60 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
61 ; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
62 ; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
63 ; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
65 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
67 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
68 ; EG-NEXT: LSHR * [[ADDR]]
69 define void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind {
70 %c = add <1 x i32> %a, %b ; add to prevent folding into extload
71 %shl = shl <1 x i32> %c, <i32 24>
72 %ashr = ashr <1 x i32> %shl, <i32 24>
73 store <1 x i32> %ashr, <1 x i32> addrspace(1)* %out, align 4
77 ; FUNC-LABEL: @sext_in_reg_i8_to_i64
78 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
79 ; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
80 ; SI: S_MOV_B32 {{s[0-9]+}}, -1
81 ; SI: BUFFER_STORE_DWORDX2
83 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
84 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
86 ; EG-NEXT: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal
91 ;; TODO Check address computation, using | with variables in {{}} does not work,
92 ;; also the _LO/_HI order might be different
93 define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
96 %ashr = ashr i64 %shl, 56
97 store i64 %ashr, i64 addrspace(1)* %out, align 8
101 ; FUNC-LABEL: @sext_in_reg_i16_to_i64
102 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
103 ; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]]
104 ; SI: S_MOV_B32 {{s[0-9]+}}, -1
105 ; SI: BUFFER_STORE_DWORDX2
107 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
108 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
110 ; EG-NEXT: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal
111 ; EG: ASHR [[RES_HI]]
115 ;; TODO Check address computation, using | with variables in {{}} does not work,
116 ;; also the _LO/_HI order might be different
117 define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
119 %shl = shl i64 %c, 48
120 %ashr = ashr i64 %shl, 48
121 store i64 %ashr, i64 addrspace(1)* %out, align 8
125 ; FUNC-LABEL: @sext_in_reg_i32_to_i64
128 ; SI: S_ADD_I32 [[ADD:s[0-9]+]],
129 ; SI: S_ASHR_I32 s{{[0-9]+}}, [[ADD]], 31
130 ; SI: BUFFER_STORE_DWORDX2
132 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
133 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
135 ; EG: ADD_INT {{\*?}} [[RES_LO]]
136 ; EG: ASHR [[RES_HI]]
140 ;; TODO Check address computation, using | with variables in {{}} does not work,
141 ;; also the _LO/_HI order might be different
142 define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
144 %shl = shl i64 %c, 32
145 %ashr = ashr i64 %shl, 32
146 store i64 %ashr, i64 addrspace(1)* %out, align 8
150 ; This is broken on Evergreen for some reason related to the <1 x i64> kernel arguments.
151 ; XFUNC-LABEL: @sext_in_reg_i8_to_v1i64
152 ; XSI: S_BFE_I32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288
153 ; XSI: S_ASHR_I32 {{v[0-9]+}}, [[EXTRACT]], 31
154 ; XSI: BUFFER_STORE_DWORD
157 ; define void @sext_in_reg_i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a, <1 x i64> %b) nounwind {
158 ; %c = add <1 x i64> %a, %b
159 ; %shl = shl <1 x i64> %c, <i64 56>
160 ; %ashr = ashr <1 x i64> %shl, <i64 56>
161 ; store <1 x i64> %ashr, <1 x i64> addrspace(1)* %out, align 8
165 ; FUNC-LABEL: @sext_in_reg_i1_in_i32_other_amount
167 ; SI: S_LSHL_B32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6
168 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG]], 7
170 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
175 ; EG: LSHR {{\*?}} [[ADDR]]
176 define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
180 store i32 %y, i32 addrspace(1)* %out
184 ; FUNC-LABEL: @sext_in_reg_v2i1_in_v2i32_other_amount
185 ; SI: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
186 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7
187 ; SI: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
188 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7
190 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
197 ; EG: LSHR {{\*?}} [[ADDR]]
198 define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
199 %c = add <2 x i32> %a, %b
200 %x = shl <2 x i32> %c, <i32 6, i32 6>
201 %y = ashr <2 x i32> %x, <i32 7, i32 7>
202 store <2 x i32> %y, <2 x i32> addrspace(1)* %out, align 2
207 ; FUNC-LABEL: @sext_in_reg_v2i1_to_v2i32
208 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
209 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
210 ; SI: BUFFER_STORE_DWORDX2
212 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
213 ; EG: BFE_INT [[RES]]
214 ; EG: BFE_INT [[RES]]
215 ; EG: LSHR {{\*?}} [[ADDR]]
216 define void @sext_in_reg_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
217 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
218 %shl = shl <2 x i32> %c, <i32 31, i32 31>
219 %ashr = ashr <2 x i32> %shl, <i32 31, i32 31>
220 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
224 ; FUNC-LABEL: @sext_in_reg_v4i1_to_v4i32
225 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
226 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
227 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
228 ; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
229 ; SI: BUFFER_STORE_DWORDX4
231 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
232 ; EG: BFE_INT [[RES]]
233 ; EG: BFE_INT [[RES]]
234 ; EG: BFE_INT [[RES]]
235 ; EG: BFE_INT [[RES]]
236 ; EG: LSHR {{\*?}} [[ADDR]]
237 define void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
238 %c = add <4 x i32> %a, %b ; add to prevent folding into extload
239 %shl = shl <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
240 %ashr = ashr <4 x i32> %shl, <i32 31, i32 31, i32 31, i32 31>
241 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
245 ; FUNC-LABEL: @sext_in_reg_v2i8_to_v2i32
246 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
247 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
248 ; SI: BUFFER_STORE_DWORDX2
250 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
251 ; EG: BFE_INT [[RES]]
252 ; EG: BFE_INT [[RES]]
253 ; EG: LSHR {{\*?}} [[ADDR]]
254 define void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
255 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
256 %shl = shl <2 x i32> %c, <i32 24, i32 24>
257 %ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
258 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
262 ; FUNC-LABEL: @sext_in_reg_v4i8_to_v4i32
263 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
264 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
265 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
266 ; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
267 ; SI: BUFFER_STORE_DWORDX4
269 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
270 ; EG: BFE_INT [[RES]]
271 ; EG: BFE_INT [[RES]]
272 ; EG: BFE_INT [[RES]]
273 ; EG: BFE_INT [[RES]]
274 ; EG: LSHR {{\*?}} [[ADDR]]
275 define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
276 %c = add <4 x i32> %a, %b ; add to prevent folding into extload
277 %shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
278 %ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
279 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
283 ; FUNC-LABEL: @sext_in_reg_v2i16_to_v2i32
284 ; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}}
285 ; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}}
286 ; SI: BUFFER_STORE_DWORDX2
288 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
289 ; EG: BFE_INT [[RES]]
290 ; EG: BFE_INT [[RES]]
291 ; EG: LSHR {{\*?}} [[ADDR]]
292 define void @sext_in_reg_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
293 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
294 %shl = shl <2 x i32> %c, <i32 16, i32 16>
295 %ashr = ashr <2 x i32> %shl, <i32 16, i32 16>
296 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
300 ; FUNC-LABEL: @testcase
301 define void @testcase(i8 addrspace(1)* %out, i8 %a) nounwind {
302 %and_a_1 = and i8 %a, 1
303 %cmp_eq = icmp eq i8 %and_a_1, 0
304 %cmp_slt = icmp slt i8 %a, 0
305 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
306 %sel1 = select i1 %cmp_eq, i8 0, i8 %a
307 %xor = xor i8 %sel0, %sel1
308 store i8 %xor, i8 addrspace(1)* %out
312 ; FUNC-LABEL: @testcase_3
313 define void @testcase_3(i8 addrspace(1)* %out, i8 %a) nounwind {
314 %and_a_1 = and i8 %a, 1
315 %cmp_eq = icmp eq i8 %and_a_1, 0
316 %cmp_slt = icmp slt i8 %a, 0
317 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
318 %sel1 = select i1 %cmp_eq, i8 0, i8 %a
319 %xor = xor i8 %sel0, %sel1
320 store i8 %xor, i8 addrspace(1)* %out
324 ; FUNC-LABEL: @vgpr_sext_in_reg_v4i8_to_v4i32
325 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
326 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
327 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
328 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
329 define void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind {
330 %loada = load <4 x i32> addrspace(1)* %a, align 16
331 %loadb = load <4 x i32> addrspace(1)* %b, align 16
332 %c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload
333 %shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
334 %ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
335 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
339 ; FUNC-LABEL: @vgpr_sext_in_reg_v4i16_to_v4i32
340 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16
341 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16
342 define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind {
343 %loada = load <4 x i32> addrspace(1)* %a, align 16
344 %loadb = load <4 x i32> addrspace(1)* %b, align 16
345 %c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload
346 %shl = shl <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16>
347 %ashr = ashr <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>
348 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
352 ; FIXME: The BFE should really be eliminated. I think it should happen
353 ; when computeMaskedBitsForTargetNode is implemented for imax.
355 ; FUNC-LABEL: @sext_in_reg_to_illegal_type
356 ; SI: BUFFER_LOAD_SBYTE
359 ; SI: BUFFER_STORE_SHORT
360 define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
361 %tmp5 = load i8 addrspace(1)* %src, align 1
362 %tmp2 = sext i8 %tmp5 to i32
363 %tmp3 = tail call i32 @llvm.AMDGPU.imax(i32 %tmp2, i32 0) nounwind readnone
364 %tmp4 = trunc i32 %tmp3 to i8
365 %tmp6 = sext i8 %tmp4 to i16
366 store i16 %tmp6, i16 addrspace(1)* %out, align 2