1 ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc < %s -march=r600 -mcpu=cypress | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4 declare i32 @llvm.AMDGPU.imax(i32, i32) nounwind readnone
7 ; FUNC-LABEL: @sext_in_reg_i1_i32
8 ; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
9 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[ARG]], 0, 1
10 ; SI: BUFFER_STORE_DWORD [[EXTRACT]],
13 define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) {
14 %shl = shl i32 %in, 31
15 %sext = ashr i32 %shl, 31
16 store i32 %sext, i32 addrspace(1)* %out
20 ; FUNC-LABEL: @sext_in_reg_i8_to_i32
21 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
22 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 8
23 ; SI: BUFFER_STORE_DWORD [[EXTRACT]],
26 define void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
27 %c = add i32 %a, %b ; add to prevent folding into extload
29 %ashr = ashr i32 %shl, 24
30 store i32 %ashr, i32 addrspace(1)* %out, align 4
34 ; FUNC-LABEL: @sext_in_reg_i16_to_i32
35 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
36 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 16
37 ; SI: BUFFER_STORE_DWORD [[EXTRACT]],
40 define void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
41 %c = add i32 %a, %b ; add to prevent folding into extload
43 %ashr = ashr i32 %shl, 16
44 store i32 %ashr, i32 addrspace(1)* %out, align 4
48 ; FUNC-LABEL: @sext_in_reg_i8_to_v1i32
49 ; SI: S_ADD_I32 [[VAL:s[0-9]+]],
50 ; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 8
51 ; SI: BUFFER_STORE_DWORD [[EXTRACT]],
54 define void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind {
55 %c = add <1 x i32> %a, %b ; add to prevent folding into extload
56 %shl = shl <1 x i32> %c, <i32 24>
57 %ashr = ashr <1 x i32> %shl, <i32 24>
58 store <1 x i32> %ashr, <1 x i32> addrspace(1)* %out, align 4
62 ; FUNC-LABEL: @sext_in_reg_i8_to_i64
63 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
64 ; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
65 ; SI: BUFFER_STORE_DWORD
69 define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
72 %ashr = ashr i64 %shl, 56
73 store i64 %ashr, i64 addrspace(1)* %out, align 8
77 ; FUNC-LABEL: @sext_in_reg_i16_to_i64
78 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 16
79 ; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
80 ; SI: BUFFER_STORE_DWORD
84 define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
87 %ashr = ashr i64 %shl, 48
88 store i64 %ashr, i64 addrspace(1)* %out, align 8
92 ; FUNC-LABEL: @sext_in_reg_i32_to_i64
96 ; SI-NEXT: S_ASHR_I32 s{{[0-9]+}}, s{{[0-9]+}}, 31
97 ; SI: BUFFER_STORE_DWORDX2
98 define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
100 %shl = shl i64 %c, 32
101 %ashr = ashr i64 %shl, 32
102 store i64 %ashr, i64 addrspace(1)* %out, align 8
106 ; This is broken on Evergreen for some reason related to the <1 x i64> kernel arguments.
107 ; XFUNC-LABEL: @sext_in_reg_i8_to_v1i64
108 ; XSI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
109 ; XSI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
110 ; XSI: BUFFER_STORE_DWORD
113 ; define void @sext_in_reg_i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a, <1 x i64> %b) nounwind {
114 ; %c = add <1 x i64> %a, %b
115 ; %shl = shl <1 x i64> %c, <i64 56>
116 ; %ashr = ashr <1 x i64> %shl, <i64 56>
117 ; store <1 x i64> %ashr, <1 x i64> addrspace(1)* %out, align 8
121 ; FUNC-LABEL: @sext_in_reg_i1_in_i32_other_amount
123 ; SI: S_LSHL_B32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6
124 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG]], 7
126 define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
130 store i32 %y, i32 addrspace(1)* %out
134 ; FUNC-LABEL: @sext_in_reg_v2i1_in_v2i32_other_amount
135 ; SI: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
136 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7
137 ; SI: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
138 ; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7
140 define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
141 %c = add <2 x i32> %a, %b
142 %x = shl <2 x i32> %c, <i32 6, i32 6>
143 %y = ashr <2 x i32> %x, <i32 7, i32 7>
144 store <2 x i32> %y, <2 x i32> addrspace(1)* %out, align 2
149 ; FUNC-LABEL: @sext_in_reg_v2i1_to_v2i32
150 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
151 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
152 ; SI: BUFFER_STORE_DWORDX2
155 define void @sext_in_reg_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
156 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
157 %shl = shl <2 x i32> %c, <i32 31, i32 31>
158 %ashr = ashr <2 x i32> %shl, <i32 31, i32 31>
159 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
163 ; FUNC-LABEL: @sext_in_reg_v4i1_to_v4i32
164 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
165 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
166 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
167 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 1
168 ; SI: BUFFER_STORE_DWORDX4
174 define void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
175 %c = add <4 x i32> %a, %b ; add to prevent folding into extload
176 %shl = shl <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
177 %ashr = ashr <4 x i32> %shl, <i32 31, i32 31, i32 31, i32 31>
178 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
182 ; FUNC-LABEL: @sext_in_reg_v2i8_to_v2i32
183 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
184 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
185 ; SI: BUFFER_STORE_DWORDX2
189 define void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
190 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
191 %shl = shl <2 x i32> %c, <i32 24, i32 24>
192 %ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
193 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
197 ; FUNC-LABEL: @sext_in_reg_v4i8_to_v4i32
198 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
199 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
200 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
201 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
202 ; SI: BUFFER_STORE_DWORDX4
208 define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
209 %c = add <4 x i32> %a, %b ; add to prevent folding into extload
210 %shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
211 %ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
212 store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
216 ; FUNC-LABEL: @sext_in_reg_v2i16_to_v2i32
217 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
218 ; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
219 ; SI: BUFFER_STORE_DWORDX2
223 define void @sext_in_reg_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
224 %c = add <2 x i32> %a, %b ; add to prevent folding into extload
225 %shl = shl <2 x i32> %c, <i32 24, i32 24>
226 %ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
227 store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
231 ; FUNC-LABEL: @testcase
232 define void @testcase(i8 addrspace(1)* %out, i8 %a) nounwind {
233 %and_a_1 = and i8 %a, 1
234 %cmp_eq = icmp eq i8 %and_a_1, 0
235 %cmp_slt = icmp slt i8 %a, 0
236 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
237 %sel1 = select i1 %cmp_eq, i8 0, i8 %a
238 %xor = xor i8 %sel0, %sel1
239 store i8 %xor, i8 addrspace(1)* %out
243 ; FUNC-LABEL: @testcase_3
244 define void @testcase_3(i8 addrspace(1)* %out, i8 %a) nounwind {
245 %and_a_1 = and i8 %a, 1
246 %cmp_eq = icmp eq i8 %and_a_1, 0
247 %cmp_slt = icmp slt i8 %a, 0
248 %sel0 = select i1 %cmp_slt, i8 0, i8 %a
249 %sel1 = select i1 %cmp_eq, i8 0, i8 %a
250 %xor = xor i8 %sel0, %sel1
251 store i8 %xor, i8 addrspace(1)* %out
255 ; FIXME: The BFE should really be eliminated. I think it should happen
256 ; when computeMaskedBitsForTargetNode is implemented for imax.
258 ; FUNC-LABEL: @sext_in_reg_to_illegal_type
259 ; SI: BUFFER_LOAD_SBYTE
262 ; SI: BUFFER_STORE_SHORT
263 define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
264 %tmp5 = load i8 addrspace(1)* %src, align 1
265 %tmp2 = sext i8 %tmp5 to i32
266 %tmp3 = tail call i32 @llvm.AMDGPU.imax(i32 %tmp2, i32 0) nounwind readnone
267 %tmp4 = trunc i32 %tmp3 to i8
268 %tmp6 = sext i8 %tmp4 to i16
269 store i16 %tmp6, i16 addrspace(1)* %out, align 2