1 ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
3 ; This test checks that no VGPR to SGPR copies are created by the register
6 ; CHECK: S_BUFFER_LOAD_DWORD [[DST:SGPR[0-9]]], {{[SGPR_[0-9]+}}, 0
7 ; CHECK: V_MOV_B32_e32 VGPR{{[0-9]}}, [[DST]]
9 define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
11 %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
12 %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
13 %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
14 %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
15 %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
16 %25 = fptosi float %23 to i32
17 %26 = icmp ne i32 %25, 0
18 br i1 %26, label %ENDIF, label %ELSE
20 ELSE: ; preds = %main_body
21 %27 = fsub float -0.000000e+00, %22
24 ENDIF: ; preds = %main_body, %ELSE
25 %temp.0 = phi float [ %27, %ELSE ], [ %22, %main_body ]
26 %28 = fadd float %temp.0, %24
27 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %28, float %28, float 0.000000e+00, float 1.000000e+00)
31 ; We just want ot make sure the program doesn't crash
34 define void @loop(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
36 %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
37 %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
38 %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
39 %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
40 %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
41 %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
42 %26 = fptosi float %25 to i32
43 %27 = bitcast i32 %26 to float
44 %28 = bitcast float %27 to i32
47 LOOP: ; preds = %ENDIF, %main_body
48 %temp4.0 = phi float [ %22, %main_body ], [ %temp5.0, %ENDIF ]
49 %temp5.0 = phi float [ %23, %main_body ], [ %temp6.0, %ENDIF ]
50 %temp6.0 = phi float [ %24, %main_body ], [ %temp4.0, %ENDIF ]
51 %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %37, %ENDIF ]
52 %29 = bitcast float %temp8.0 to i32
53 %30 = icmp sge i32 %29, %28
54 %31 = sext i1 %30 to i32
55 %32 = bitcast i32 %31 to float
56 %33 = bitcast float %32 to i32
57 %34 = icmp ne i32 %33, 0
58 br i1 %34, label %IF, label %ENDIF
61 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00)
64 ENDIF: ; preds = %LOOP
65 %35 = bitcast float %temp8.0 to i32
67 %37 = bitcast i32 %36 to float
71 ; Function Attrs: nounwind readnone
72 declare float @llvm.SI.load.const(<16 x i8>, i32) #1
74 ; Function Attrs: readonly
75 declare float @fabs(float) #2
77 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
79 attributes #0 = { "ShaderType"="0" }
80 attributes #1 = { nounwind readnone }
81 attributes #2 = { readonly }
83 !0 = metadata !{metadata !"const", null, i32 1}