2 ; Enable when patch to perform shl + add constant generic DAG combiner patch is in.
4 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
6 ; Test that doing a shift of a pointer with a constant add will be
7 ; folded into the constant offset addressing mode even if the add has
8 ; multiple uses. This is relevant to accessing 2 separate, adjacent
12 declare i32 @llvm.r600.read.tidig.x() #1
14 @lds0 = addrspace(3) global [512 x float] zeroinitializer, align 4
15 @lds1 = addrspace(3) global [512 x float] zeroinitializer, align 4
18 ; Make sure the (add tid, 2) << 2 gets folded into the ds's offset as (tid << 2) + 8
20 ; SI-LABEL: @load_shl_base_lds_0
21 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
22 ; SI: DS_READ_B32 {{v[0-9]+}}, [[PTR]], 0x8, [M0]
24 define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
25 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
26 %idx.0 = add nsw i32 %tid.x, 2
27 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
28 %val0 = load float addrspace(3)* %arrayidx0, align 4
29 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
30 store float %val0, float addrspace(1)* %out
34 ; Make sure once the first use is folded into the addressing mode, the
35 ; remaining add use goes through the normal shl + add constant fold.
37 ; SI-LABEL: @load_shl_base_lds_1
38 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
39 ; SI: DS_READ_B32 [[RESULT:v[0-9]+]], [[PTR]], 0x8, [M0]
40 ; SI: V_ADD_I32_e32 [[ADDUSE:v[0-9]+]], 8, v{{[0-9]+}}
41 ; SI-DAG: BUFFER_STORE_DWORD [[RESULT]]
42 ; SI-DAG: BUFFER_STORE_DWORD [[ADDUSE]]
44 define void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
45 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
46 %idx.0 = add nsw i32 %tid.x, 2
47 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
48 %val0 = load float addrspace(3)* %arrayidx0, align 4
49 %shl_add_use = shl i32 %idx.0, 2
50 store i32 %shl_add_use, i32 addrspace(1)* %add_use, align 4
51 store float %val0, float addrspace(1)* %out
55 @maxlds = addrspace(3) global [65536 x i8] zeroinitializer, align 4
57 ; SI-LABEL: @load_shl_base_lds_max_offset
58 ; SI: DS_READ_U8 v{{[0-9]+}}, v{{[0-9]+}}, 0xffff
60 define void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %lds, i32 addrspace(1)* %add_use) #0 {
61 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
62 %idx.0 = add nsw i32 %tid.x, 65535
63 %arrayidx0 = getelementptr inbounds [65536 x i8] addrspace(3)* @maxlds, i32 0, i32 %idx.0
64 %val0 = load i8 addrspace(3)* %arrayidx0
65 store i32 %idx.0, i32 addrspace(1)* %add_use
66 store i8 %val0, i8 addrspace(1)* %out
70 ; The two globals are placed adjacent in memory, so the same base
71 ; pointer can be used with an offset into the second one.
73 ; SI-LABEL: @load_shl_base_lds_2
74 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
75 ; SI-NEXT: DS_READ_B32 {{v[0-9]+}}, [[PTR]], 0x100, [M0]
76 ; SI-NEXT: DS_READ_B32 {{v[0-9]+}}, [[PTR]], 0x900, [M0]
78 define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 {
79 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
80 %idx.0 = add nsw i32 %tid.x, 64
81 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
82 %val0 = load float addrspace(3)* %arrayidx0, align 4
83 %arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds1, i32 0, i32 %idx.0
84 %val1 = load float addrspace(3)* %arrayidx1, align 4
85 %sum = fadd float %val0, %val1
86 store float %sum, float addrspace(1)* %out, align 4
90 ; SI-LABEL: @store_shl_base_lds_0
91 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
92 ; SI: DS_WRITE_B32 [[PTR]], {{v[0-9]+}}, 0x8 [M0]
94 define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
95 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
96 %idx.0 = add nsw i32 %tid.x, 2
97 %arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
98 store float 1.0, float addrspace(3)* %arrayidx0, align 4
99 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
104 ; --------------------------------------------------------------------------------
107 @lds2 = addrspace(3) global [512 x i32] zeroinitializer, align 4
109 ; define void @atomic_load_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
110 ; %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
111 ; %idx.0 = add nsw i32 %tid.x, 2
112 ; %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
113 ; %val = load atomic i32 addrspace(3)* %arrayidx0 seq_cst, align 4
114 ; store i32 %val, i32 addrspace(1)* %out, align 4
115 ; store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
120 ; SI-LABEL: @atomic_cmpxchg_shl_base_lds_0
121 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
122 ; SI: DS_CMPST_RTN_B32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, {{v[0-9]+}}, 0x8
124 define void @atomic_cmpxchg_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use, i32 %swap) #0 {
125 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
126 %idx.0 = add nsw i32 %tid.x, 2
127 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
128 %pair = cmpxchg i32 addrspace(3)* %arrayidx0, i32 7, i32 %swap seq_cst monotonic
129 %result = extractvalue { i32, i1 } %pair, 0
130 store i32 %result, i32 addrspace(1)* %out, align 4
131 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
135 ; SI-LABEL: @atomic_swap_shl_base_lds_0
136 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
137 ; SI: DS_WRXCHG_RTN_B32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, 0x8
139 define void @atomic_swap_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
140 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
141 %idx.0 = add nsw i32 %tid.x, 2
142 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
143 %val = atomicrmw xchg i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
144 store i32 %val, i32 addrspace(1)* %out, align 4
145 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
149 ; SI-LABEL: @atomic_add_shl_base_lds_0
150 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
151 ; SI: DS_ADD_RTN_U32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, 0x8
153 define void @atomic_add_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
154 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
155 %idx.0 = add nsw i32 %tid.x, 2
156 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
157 %val = atomicrmw add i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
158 store i32 %val, i32 addrspace(1)* %out, align 4
159 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
163 ; SI-LABEL: @atomic_sub_shl_base_lds_0
164 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
165 ; SI: DS_SUB_RTN_U32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, 0x8
167 define void @atomic_sub_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
168 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
169 %idx.0 = add nsw i32 %tid.x, 2
170 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
171 %val = atomicrmw sub i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
172 store i32 %val, i32 addrspace(1)* %out, align 4
173 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
177 ; SI-LABEL: @atomic_and_shl_base_lds_0
178 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
179 ; SI: DS_AND_RTN_B32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, 0x8
181 define void @atomic_and_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
182 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
183 %idx.0 = add nsw i32 %tid.x, 2
184 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
185 %val = atomicrmw and i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
186 store i32 %val, i32 addrspace(1)* %out, align 4
187 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
191 ; SI-LABEL: @atomic_or_shl_base_lds_0
192 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
193 ; SI: DS_OR_RTN_B32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, 0x8
195 define void @atomic_or_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
196 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
197 %idx.0 = add nsw i32 %tid.x, 2
198 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
199 %val = atomicrmw or i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
200 store i32 %val, i32 addrspace(1)* %out, align 4
201 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
205 ; SI-LABEL: @atomic_xor_shl_base_lds_0
206 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
207 ; SI: DS_XOR_RTN_B32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, 0x8
209 define void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
210 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
211 %idx.0 = add nsw i32 %tid.x, 2
212 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
213 %val = atomicrmw xor i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
214 store i32 %val, i32 addrspace(1)* %out, align 4
215 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
219 ; define void @atomic_nand_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
220 ; %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
221 ; %idx.0 = add nsw i32 %tid.x, 2
222 ; %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
223 ; %val = atomicrmw nand i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
224 ; store i32 %val, i32 addrspace(1)* %out, align 4
225 ; store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
229 ; SI-LABEL: @atomic_min_shl_base_lds_0
230 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
231 ; SI: DS_MIN_RTN_I32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, 0x8
233 define void @atomic_min_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
234 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
235 %idx.0 = add nsw i32 %tid.x, 2
236 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
237 %val = atomicrmw min i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
238 store i32 %val, i32 addrspace(1)* %out, align 4
239 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
243 ; SI-LABEL: @atomic_max_shl_base_lds_0
244 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
245 ; SI: DS_MAX_RTN_I32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, 0x8
247 define void @atomic_max_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
248 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
249 %idx.0 = add nsw i32 %tid.x, 2
250 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
251 %val = atomicrmw max i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
252 store i32 %val, i32 addrspace(1)* %out, align 4
253 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
257 ; SI-LABEL: @atomic_umin_shl_base_lds_0
258 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
259 ; SI: DS_MIN_RTN_U32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, 0x8
261 define void @atomic_umin_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
262 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
263 %idx.0 = add nsw i32 %tid.x, 2
264 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
265 %val = atomicrmw umin i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
266 store i32 %val, i32 addrspace(1)* %out, align 4
267 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
271 ; SI-LABEL: @atomic_umax_shl_base_lds_0
272 ; SI: V_LSHLREV_B32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
273 ; SI: DS_MAX_RTN_U32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, 0x8
275 define void @atomic_umax_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
276 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
277 %idx.0 = add nsw i32 %tid.x, 2
278 %arrayidx0 = getelementptr inbounds [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0
279 %val = atomicrmw umax i32 addrspace(3)* %arrayidx0, i32 3 seq_cst
280 store i32 %val, i32 addrspace(1)* %out, align 4
281 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
285 attributes #0 = { nounwind }
286 attributes #1 = { nounwind readnone }