1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s
2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK --check-prefix=FUNC %s
3 ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s
5 ;===------------------------------------------------------------------------===;
7 ;===------------------------------------------------------------------------===;
8 ; FUNC-LABEL: @store_i1
9 ; EG-CHECK: MEM_RAT MSKOR
10 ; SI-CHECK: BUFFER_STORE_BYTE
11 define void @store_i1(i1 addrspace(1)* %out) {
13 store i1 true, i1 addrspace(1)* %out
18 ; EG-CHECK-LABEL: @store_i8
19 ; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
20 ; EG-CHECK: VTX_READ_8 [[VAL:T[0-9]\.X]], [[VAL]]
21 ; IG 0: Get the byte index and truncate the value
22 ; EG-CHECK: AND_INT T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
23 ; EG-CHECK-NEXT: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.y
24 ; EG-CHECK-NEXT: 3(4.203895e-45), 255(3.573311e-43)
25 ; IG 1: Truncate the calculated the shift amount for the mask
26 ; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
28 ; IG 2: Shift the value and the mask
29 ; EG-CHECK: LSHL T[[RW_GPR]].X, T{{[0-9]}}.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]]
30 ; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
32 ; IG 3: Initialize the Y and Z channels to zero
33 ; XXX: An optimal scheduler should merge this into one of the prevous IGs.
34 ; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
35 ; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
37 ; SI-CHECK-LABEL: @store_i8
38 ; SI-CHECK: BUFFER_STORE_BYTE
40 define void @store_i8(i8 addrspace(1)* %out, i8 %in) {
42 store i8 %in, i8 addrspace(1)* %out
47 ; EG-CHECK-LABEL: @store_i16
48 ; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
49 ; EG-CHECK: VTX_READ_16 [[VAL:T[0-9]\.X]], [[VAL]]
50 ; IG 0: Get the byte index and truncate the value
51 ; EG-CHECK: AND_INT T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
52 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.y
53 ; EG-CHECK-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
54 ; IG 1: Truncate the calculated the shift amount for the mask
55 ; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
57 ; IG 2: Shift the value and the mask
58 ; EG-CHECK: LSHL T[[RW_GPR]].X, T{{[0-9]}}.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]]
59 ; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
60 ; EG-CHECK-NEXT: 65535
61 ; IG 3: Initialize the Y and Z channels to zero
62 ; XXX: An optimal scheduler should merge this into one of the prevous IGs.
63 ; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
64 ; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
66 ; SI-CHECK-LABEL: @store_i16
67 ; SI-CHECK: BUFFER_STORE_SHORT
68 define void @store_i16(i16 addrspace(1)* %out, i16 %in) {
70 store i16 %in, i16 addrspace(1)* %out
74 ; EG-CHECK-LABEL: @store_v2i8
75 ; EG-CHECK: MEM_RAT MSKOR
76 ; EG-CHECK-NOT: MEM_RAT MSKOR
77 ; SI-CHECK-LABEL: @store_v2i8
78 ; SI-CHECK: BUFFER_STORE_BYTE
79 ; SI-CHECK: BUFFER_STORE_BYTE
80 define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
82 %0 = trunc <2 x i32> %in to <2 x i8>
83 store <2 x i8> %0, <2 x i8> addrspace(1)* %out
88 ; EG-CHECK-LABEL: @store_v2i16
89 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
90 ; CM-CHECK-LABEL: @store_v2i16
91 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
92 ; SI-CHECK-LABEL: @store_v2i16
93 ; SI-CHECK: BUFFER_STORE_SHORT
94 ; SI-CHECK: BUFFER_STORE_SHORT
95 define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
97 %0 = trunc <2 x i32> %in to <2 x i16>
98 store <2 x i16> %0, <2 x i16> addrspace(1)* %out
102 ; EG-CHECK-LABEL: @store_v4i8
103 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
104 ; CM-CHECK-LABEL: @store_v4i8
105 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
106 ; SI-CHECK-LABEL: @store_v4i8
107 ; SI-CHECK: BUFFER_STORE_BYTE
108 ; SI-CHECK: BUFFER_STORE_BYTE
109 ; SI-CHECK: BUFFER_STORE_BYTE
110 ; SI-CHECK: BUFFER_STORE_BYTE
111 define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
113 %0 = trunc <4 x i32> %in to <4 x i8>
114 store <4 x i8> %0, <4 x i8> addrspace(1)* %out
118 ; floating-point store
119 ; EG-CHECK-LABEL: @store_f32
120 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
121 ; CM-CHECK-LABEL: @store_f32
122 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
123 ; SI-CHECK-LABEL: @store_f32
124 ; SI-CHECK: BUFFER_STORE_DWORD
126 define void @store_f32(float addrspace(1)* %out, float %in) {
127 store float %in, float addrspace(1)* %out
131 ; EG-CHECK-LABEL: @store_v4i16
132 ; EG-CHECK: MEM_RAT MSKOR
133 ; EG-CHECK: MEM_RAT MSKOR
134 ; EG-CHECK: MEM_RAT MSKOR
135 ; EG-CHECK: MEM_RAT MSKOR
136 ; EG-CHECK-NOT: MEM_RAT MSKOR
137 ; SI-CHECK-LABEL: @store_v4i16
138 ; SI-CHECK: BUFFER_STORE_SHORT
139 ; SI-CHECK: BUFFER_STORE_SHORT
140 ; SI-CHECK: BUFFER_STORE_SHORT
141 ; SI-CHECK: BUFFER_STORE_SHORT
142 ; SI-CHECK-NOT: BUFFER_STORE_BYTE
143 define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) {
145 %0 = trunc <4 x i32> %in to <4 x i16>
146 store <4 x i16> %0, <4 x i16> addrspace(1)* %out
150 ; vec2 floating-point stores
151 ; EG-CHECK-LABEL: @store_v2f32
152 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
153 ; CM-CHECK-LABEL: @store_v2f32
154 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
155 ; SI-CHECK-LABEL: @store_v2f32
156 ; SI-CHECK: BUFFER_STORE_DWORDX2
158 define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
160 %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
161 %1 = insertelement <2 x float> %0, float %b, i32 1
162 store <2 x float> %1, <2 x float> addrspace(1)* %out
166 ; EG-CHECK-LABEL: @store_v4i32
167 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
168 ; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW
169 ; CM-CHECK-LABEL: @store_v4i32
170 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
171 ; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD
172 ; SI-CHECK-LABEL: @store_v4i32
173 ; SI-CHECK: BUFFER_STORE_DWORDX4
174 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
176 store <4 x i32> %in, <4 x i32> addrspace(1)* %out
180 ;===------------------------------------------------------------------------===;
181 ; Local Address Space
182 ;===------------------------------------------------------------------------===;
184 ; FUNC-LABEL: @store_local_i1
185 ; EG-CHECK: LDS_BYTE_WRITE
186 ; SI-CHECK: DS_WRITE_B8
187 define void @store_local_i1(i1 addrspace(3)* %out) {
189 store i1 true, i1 addrspace(3)* %out
193 ; EG-CHECK-LABEL: @store_local_i8
194 ; EG-CHECK: LDS_BYTE_WRITE
195 ; SI-CHECK-LABEL: @store_local_i8
196 ; SI-CHECK: DS_WRITE_B8
197 define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) {
198 store i8 %in, i8 addrspace(3)* %out
202 ; EG-CHECK-LABEL: @store_local_i16
203 ; EG-CHECK: LDS_SHORT_WRITE
204 ; SI-CHECK-LABEL: @store_local_i16
205 ; SI-CHECK: DS_WRITE_B16
206 define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) {
207 store i16 %in, i16 addrspace(3)* %out
211 ; EG-CHECK-LABEL: @store_local_v2i16
212 ; EG-CHECK: LDS_WRITE
213 ; CM-CHECK-LABEL: @store_local_v2i16
214 ; CM-CHECK: LDS_WRITE
215 ; SI-CHECK-LABEL: @store_local_v2i16
216 ; SI-CHECK: DS_WRITE_B16
217 ; SI-CHECK: DS_WRITE_B16
218 define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) {
220 store <2 x i16> %in, <2 x i16> addrspace(3)* %out
224 ; EG-CHECK-LABEL: @store_local_v4i8
225 ; EG-CHECK: LDS_WRITE
226 ; CM-CHECK-LABEL: @store_local_v4i8
227 ; CM-CHECK: LDS_WRITE
228 ; SI-CHECK-LABEL: @store_local_v4i8
229 ; SI-CHECK: DS_WRITE_B8
230 ; SI-CHECK: DS_WRITE_B8
231 ; SI-CHECK: DS_WRITE_B8
232 ; SI-CHECK: DS_WRITE_B8
233 define void @store_local_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> %in) {
235 store <4 x i8> %in, <4 x i8> addrspace(3)* %out
239 ; EG-CHECK-LABEL: @store_local_v2i32
240 ; EG-CHECK: LDS_WRITE
241 ; EG-CHECK: LDS_WRITE
242 ; CM-CHECK-LABEL: @store_local_v2i32
243 ; CM-CHECK: LDS_WRITE
244 ; CM-CHECK: LDS_WRITE
245 ; SI-CHECK-LABEL: @store_local_v2i32
246 ; SI-CHECK: DS_WRITE_B32
247 ; SI-CHECK: DS_WRITE_B32
248 define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) {
250 store <2 x i32> %in, <2 x i32> addrspace(3)* %out
254 ; EG-CHECK-LABEL: @store_local_v4i32
255 ; EG-CHECK: LDS_WRITE
256 ; EG-CHECK: LDS_WRITE
257 ; EG-CHECK: LDS_WRITE
258 ; EG-CHECK: LDS_WRITE
259 ; CM-CHECK-LABEL: @store_local_v4i32
260 ; CM-CHECK: LDS_WRITE
261 ; CM-CHECK: LDS_WRITE
262 ; CM-CHECK: LDS_WRITE
263 ; CM-CHECK: LDS_WRITE
264 ; SI-CHECK-LABEL: @store_local_v4i32
265 ; SI-CHECK: DS_WRITE_B32
266 ; SI-CHECK: DS_WRITE_B32
267 ; SI-CHECK: DS_WRITE_B32
268 ; SI-CHECK: DS_WRITE_B32
269 define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) {
271 store <4 x i32> %in, <4 x i32> addrspace(3)* %out
275 ; The stores in this function are combined by the optimizer to create a
276 ; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
277 ; should not try to split the 64-bit store back into 2 32-bit stores.
279 ; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
280 ; be two 32-bit stores.
282 ; EG-CHECK-LABEL: @vecload2
283 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
284 ; CM-CHECK-LABEL: @vecload2
285 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
286 ; SI-CHECK-LABEL: @vecload2
287 ; SI-CHECK: BUFFER_STORE_DWORDX2
288 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
290 %0 = load i32 addrspace(2)* %mem, align 4
291 %arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
292 %1 = load i32 addrspace(2)* %arrayidx1.i, align 4
293 store i32 %0, i32 addrspace(1)* %out, align 4
294 %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
295 store i32 %1, i32 addrspace(1)* %arrayidx1, align 4
299 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }