1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
3 ; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
5 ;===------------------------------------------------------------------------===;
7 ;===------------------------------------------------------------------------===;
11 ; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
12 ; EG-CHECK: VTX_READ_8 [[VAL:T[0-9]\.X]], [[VAL]]
13 ; IG 0: Get the byte index
14 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
16 ; IG 1: Truncate the value and calculated the shift amount for the mask
17 ; EG-CHECK: AND_INT T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.x
18 ; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.y
19 ; EG-CHECK: 255(3.573311e-43), 3
20 ; IG 2: Shift the value and the mask
21 ; EG-CHECK: LSHL T[[RW_GPR]].X, PV.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]]
22 ; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
24 ; IG 3: Initialize the Y and Z channels to zero
25 ; XXX: An optimal scheduler should merge this into one of the prevous IGs.
26 ; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
27 ; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
30 ; SI-CHECK: BUFFER_STORE_BYTE
32 define void @store_i8(i8 addrspace(1)* %out, i8 %in) {
34 store i8 %in, i8 addrspace(1)* %out
39 ; EG-CHECK: @store_i16
40 ; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
41 ; EG-CHECK: VTX_READ_16 [[VAL:T[0-9]\.X]], [[VAL]]
42 ; IG 0: Get the byte index
43 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
45 ; IG 1: Truncate the value and calculated the shift amount for the mask
46 ; EG-CHECK: AND_INT T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.x
47 ; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.y
48 ; EG-CHECK: 65535(9.183409e-41), 3
49 ; IG 2: Shift the value and the mask
50 ; EG-CHECK: LSHL T[[RW_GPR]].X, PV.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]]
51 ; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
52 ; EG-CHECK-NEXT: 65535
53 ; IG 3: Initialize the Y and Z channels to zero
54 ; XXX: An optimal scheduler should merge this into one of the prevous IGs.
55 ; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
56 ; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
58 ; SI-CHECK: @store_i16
59 ; SI-CHECK: BUFFER_STORE_SHORT
60 define void @store_i16(i16 addrspace(1)* %out, i16 %in) {
62 store i16 %in, i16 addrspace(1)* %out
66 ; EG-CHECK: @store_v2i8
67 ; EG-CHECK: MEM_RAT MSKOR
68 ; EG-CHECK-NOT: MEM_RAT MSKOR
69 ; SI-CHECK: @store_v2i8
70 ; SI-CHECK: BUFFER_STORE_BYTE
71 ; SI-CHECK: BUFFER_STORE_BYTE
72 define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
74 %0 = trunc <2 x i32> %in to <2 x i8>
75 store <2 x i8> %0, <2 x i8> addrspace(1)* %out
80 ; EG-CHECK: @store_v2i16
81 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
82 ; CM-CHECK: @store_v2i16
83 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
84 ; SI-CHECK: @store_v2i16
85 ; SI-CHECK: BUFFER_STORE_DWORD
86 define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
88 %0 = trunc <2 x i32> %in to <2 x i16>
89 store <2 x i16> %0, <2 x i16> addrspace(1)* %out
93 ; EG-CHECK: @store_v4i8
94 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
95 ; CM-CHECK: @store_v4i8
96 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
97 ; SI-CHECK: @store_v4i8
98 ; SI-CHECK: BUFFER_STORE_BYTE
99 ; SI-CHECK: BUFFER_STORE_BYTE
100 ; SI-CHECK: BUFFER_STORE_BYTE
101 ; SI-CHECK: BUFFER_STORE_BYTE
102 define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
104 %0 = trunc <4 x i32> %in to <4 x i8>
105 store <4 x i8> %0, <4 x i8> addrspace(1)* %out
109 ; floating-point store
110 ; EG-CHECK: @store_f32
111 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
112 ; CM-CHECK: @store_f32
113 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
114 ; SI-CHECK: @store_f32
115 ; SI-CHECK: BUFFER_STORE_DWORD
117 define void @store_f32(float addrspace(1)* %out, float %in) {
118 store float %in, float addrspace(1)* %out
122 ; EG-CHECK: @store_v4i16
123 ; EG-CHECK: MEM_RAT MSKOR
124 ; EG-CHECK: MEM_RAT MSKOR
125 ; EG-CHECK: MEM_RAT MSKOR
126 ; EG-CHECK: MEM_RAT MSKOR
127 ; EG-CHECK-NOT: MEM_RAT MSKOR
128 ; SI-CHECK: @store_v4i16
129 ; SI-CHECK: BUFFER_STORE_SHORT
130 ; SI-CHECK: BUFFER_STORE_SHORT
131 ; SI-CHECK: BUFFER_STORE_SHORT
132 ; SI-CHECK: BUFFER_STORE_SHORT
133 ; SI-CHECK-NOT: BUFFER_STORE_BYTE
134 define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) {
136 %0 = trunc <4 x i32> %in to <4 x i16>
137 store <4 x i16> %0, <4 x i16> addrspace(1)* %out
141 ; vec2 floating-point stores
142 ; EG-CHECK: @store_v2f32
143 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
144 ; CM-CHECK: @store_v2f32
145 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
146 ; SI-CHECK: @store_v2f32
147 ; SI-CHECK: BUFFER_STORE_DWORDX2
149 define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
151 %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
152 %1 = insertelement <2 x float> %0, float %b, i32 1
153 store <2 x float> %1, <2 x float> addrspace(1)* %out
157 ; EG-CHECK: @store_v4i32
158 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
159 ; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW
160 ; CM-CHECK: @store_v4i32
161 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
162 ; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD
163 ; SI-CHECK: @store_v4i32
164 ; SI-CHECK: BUFFER_STORE_DWORDX4
165 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
167 store <4 x i32> %in, <4 x i32> addrspace(1)* %out
171 ;===------------------------------------------------------------------------===;
172 ; Local Address Space
173 ;===------------------------------------------------------------------------===;
175 ; EG-CHECK: @store_local_v2i16
176 ; EG-CHECK: LDS_WRITE
177 ; CM-CHECK: @store_local_v2i16
178 ; CM-CHECK: LDS_WRITE
179 ; SI-CHECK: @store_local_v2i16
180 ; SI-CHECK: DS_WRITE_B32
181 define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) {
183 store <2 x i16> %in, <2 x i16> addrspace(3)* %out
187 ; EG-CHECK: @store_local_v2i32
188 ; EG-CHECK: LDS_WRITE
189 ; EG-CHECK: LDS_WRITE
190 ; CM-CHECK: @store_local_v2i32
191 ; CM-CHECK: LDS_WRITE
192 ; CM-CHECK: LDS_WRITE
193 ; SI-CHECK: @store_local_v2i32
194 ; SI-CHECK: DS_WRITE_B32
195 ; SI-CHECK: DS_WRITE_B32
196 define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) {
198 store <2 x i32> %in, <2 x i32> addrspace(3)* %out
202 ; EG-CHECK: @store_local_v4i32
203 ; EG-CHECK: LDS_WRITE
204 ; EG-CHECK: LDS_WRITE
205 ; EG-CHECK: LDS_WRITE
206 ; EG-CHECK: LDS_WRITE
207 ; CM-CHECK: @store_local_v4i32
208 ; CM-CHECK: LDS_WRITE
209 ; CM-CHECK: LDS_WRITE
210 ; CM-CHECK: LDS_WRITE
211 ; CM-CHECK: LDS_WRITE
212 ; SI-CHECK: @store_local_v4i32
213 ; SI-CHECK: DS_WRITE_B32
214 ; SI-CHECK: DS_WRITE_B32
215 ; SI-CHECK: DS_WRITE_B32
216 ; SI-CHECK: DS_WRITE_B32
217 define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) {
219 store <4 x i32> %in, <4 x i32> addrspace(3)* %out
223 ; The stores in this function are combined by the optimizer to create a
224 ; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
225 ; should not try to split the 64-bit store back into 2 32-bit stores.
227 ; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
228 ; be two 32-bit stores.
230 ; EG-CHECK: @vecload2
231 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
232 ; CM-CHECK: @vecload2
233 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
234 ; SI-CHECK: @vecload2
235 ; SI-CHECK: BUFFER_STORE_DWORDX2
236 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
238 %0 = load i32 addrspace(2)* %mem, align 4, !tbaa !5
239 %arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
240 %1 = load i32 addrspace(2)* %arrayidx1.i, align 4, !tbaa !5
241 store i32 %0, i32 addrspace(1)* %out, align 4, !tbaa !5
242 %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
243 store i32 %1, i32 addrspace(1)* %arrayidx1, align 4, !tbaa !5
247 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
249 !5 = metadata !{metadata !"int", metadata !6}
250 !6 = metadata !{metadata !"omnipotent char", metadata !7}
251 !7 = metadata !{metadata !"Simple C/C++ TBAA"}