1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
2 ;RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI %s
3 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s
5 ;EG: {{^}}test_select_v2i32:
6 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
9 ;SI: {{^}}test_select_v2i32:
10 ;SI: v_cndmask_b32_e64
11 ;SI: v_cndmask_b32_e64
13 define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
15 %0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0
16 %1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1
17 %cmp = icmp ne <2 x i32> %0, %1
18 %result = select <2 x i1> %cmp, <2 x i32> %0, <2 x i32> %1
19 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
23 ;EG: {{^}}test_select_v2f32:
24 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
25 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ;SI: {{^}}test_select_v2f32:
28 ;SI: v_cndmask_b32_e64
29 ;SI: v_cndmask_b32_e64
31 define void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) {
33 %0 = load <2 x float>, <2 x float> addrspace(1)* %in0
34 %1 = load <2 x float>, <2 x float> addrspace(1)* %in1
35 %cmp = fcmp une <2 x float> %0, %1
36 %result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1
37 store <2 x float> %result, <2 x float> addrspace(1)* %out
41 ;EG: {{^}}test_select_v4i32:
42 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
43 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
45 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
47 ;SI: {{^}}test_select_v4i32:
48 ;SI: v_cndmask_b32_e64
49 ;SI: v_cndmask_b32_e64
50 ;SI: v_cndmask_b32_e64
51 ;SI: v_cndmask_b32_e64
53 define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
55 %0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0
56 %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1
57 %cmp = icmp ne <4 x i32> %0, %1
58 %result = select <4 x i1> %cmp, <4 x i32> %0, <4 x i32> %1
59 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
63 ;EG: {{^}}test_select_v4f32:
64 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
65 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
66 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
67 ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
69 define void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) {
71 %0 = load <4 x float>, <4 x float> addrspace(1)* %in0
72 %1 = load <4 x float>, <4 x float> addrspace(1)* %in1
73 %cmp = fcmp une <4 x float> %0, %1
74 %result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1
75 store <4 x float> %result, <4 x float> addrspace(1)* %out