1 ; RUN: llc -march=sparc <%s | FileCheck %s -check-prefix=V8
2 ; RUN: llc -march=sparc -mattr=v9 <%s | FileCheck %s -check-prefix=V9
3 ; RUN: llc -mtriple=sparc64-unknown-linux <%s | FileCheck %s -check-prefix=SPARC64
6 define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline {
14 ; V9: mov{{e|ne}} %icc
16 %1 = icmp ugt i64 %0, %c
17 %2 = zext i1 %1 to i32
22 define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
24 ; V8: test_select_int_icc
27 ; V9: test_select_int_icc
30 ; V9: mov{{e|ne}} %icc
31 %0 = icmp eq i32 %a, 0
32 %1 = select i1 %0, i32 %b, i32 %c
37 define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
39 ; V8: test_select_fp_icc
42 ; V9: test_select_fp_icc
45 ; V9: fmovs{{e|ne}} %icc
46 %0 = icmp eq i32 %a, 0
47 %1 = select i1 %0, float %f1, float %f2
51 define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
53 ; V8: test_select_dfp_icc
56 ; V9: test_select_dfp_icc
59 ; V9: fmovd{{e|ne}} %icc
60 %0 = icmp eq i32 %a, 0
61 %1 = select i1 %0, double %f1, double %f2
65 define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
67 ;V8-LABEL: test_select_int_fcc:
70 ;V9-LABEL: test_select_int_fcc:
73 ;V9: mov{{e|ne}} %fcc0
74 %0 = fcmp une float %f, 0.000000e+00
75 %a.b = select i1 %0, i32 %a, i32 %b
80 define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
82 ;V8-LABEL: test_select_fp_fcc:
85 ;V9-LABEL: test_select_fp_fcc:
88 ;V9: fmovs{{e|ne}} %fcc0
89 %0 = fcmp une float %f, 0.000000e+00
90 %1 = select i1 %0, float %f1, float %f2
94 define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
96 ;V8-LABEL: test_select_dfp_fcc:
99 ;V9-LABEL: test_select_dfp_fcc:
101 ;V9-NOT: {{fbne|fbe}}
102 ;V9: fmovd{{e|ne}} %fcc0
103 %0 = fcmp une double %f, 0.000000e+00
104 %1 = select i1 %0, double %f1, double %f2
108 define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) {
110 ; V8-LABEL: test_float_cc
112 ; V8: {{fbl|fbuge}} .LBB
114 ; V8: {{fbule|fbg}} .LBB
116 ; V9-LABEL: test_float_cc
118 ; V9: {{fbl|fbuge}} .LBB
120 ; V9: {{fbule|fbg}} .LBB
122 %0 = fcmp uge double %a, 0.000000e+00
123 br i1 %0, label %loop, label %loop.2
126 %1 = icmp eq i32 %c, 10
127 br i1 %1, label %loop, label %exit.0
130 %2 = fcmp ogt double %b, 0.000000e+00
131 br i1 %2, label %exit.1, label %loop
140 ; V8-LABEL: test_adde_sube
151 ; V9-LABEL: test_adde_sube
161 ; SPARC64-LABEL: test_adde_sube
172 define void @test_adde_sube(i8* %a, i8* %b, i8* %sum, i8* %diff) {
174 %0 = bitcast i8* %a to i128*
175 %1 = bitcast i8* %b to i128*
179 %5 = bitcast i8* %sum to i128*
180 store i128 %4, i128* %5
181 tail call void asm sideeffect "", "=*m,*m"(i128 *%0, i128* %5) nounwind
184 %8 = bitcast i8* %diff to i128*
185 store i128 %7, i128* %8