1 ; Test 8-bit atomic min/max operations.
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1
5 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2
7 ; Check signed minimum.
8 ; - CHECK is for the main loop.
9 ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
10 ; RLL is set up correctly. The negation is independent of the NILL and L
12 ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
13 ; before being used, and that the low bits are set to 1. This sequence is
14 ; independent of the other loop prologue instructions.
15 define i16 @f1(i16 *%src, i16 %b) {
17 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
18 ; CHECK: nill %r2, 65532
19 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
20 ; CHECK: [[LOOP:\.[^:]*]]:
21 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
22 ; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
23 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
25 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
26 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
28 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
31 ; CHECK-SHIFT1-LABEL: f1:
32 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
33 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
35 ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
37 ; CHECK-SHIFT1: br %r14
39 ; CHECK-SHIFT2-LABEL: f1:
40 ; CHECK-SHIFT2: sll %r3, 16
42 ; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
45 ; CHECK-SHIFT2: br %r14
46 %res = atomicrmw min i16 *%src, i16 %b seq_cst
50 ; Check signed maximum.
51 define i16 @f2(i16 *%src, i16 %b) {
53 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
54 ; CHECK: nill %r2, 65532
55 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
56 ; CHECK: [[LOOP:\.[^:]*]]:
57 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
58 ; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
59 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
61 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
62 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
64 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
67 ; CHECK-SHIFT1-LABEL: f2:
68 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
69 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
71 ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
73 ; CHECK-SHIFT1: br %r14
75 ; CHECK-SHIFT2-LABEL: f2:
76 ; CHECK-SHIFT2: sll %r3, 16
78 ; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
81 ; CHECK-SHIFT2: br %r14
82 %res = atomicrmw max i16 *%src, i16 %b seq_cst
86 ; Check unsigned minimum.
87 define i16 @f3(i16 *%src, i16 %b) {
89 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
90 ; CHECK: nill %r2, 65532
91 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
92 ; CHECK: [[LOOP:\.[^:]*]]:
93 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
94 ; CHECK: clrjle [[ROT]], %r3, [[KEEP:\..*]]
95 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
97 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
98 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
100 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
103 ; CHECK-SHIFT1-LABEL: f3:
104 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
105 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
107 ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
109 ; CHECK-SHIFT1: br %r14
111 ; CHECK-SHIFT2-LABEL: f3:
112 ; CHECK-SHIFT2: sll %r3, 16
114 ; CHECK-SHIFT2: clrjle {{%r[0-9]+}}, %r3,
117 ; CHECK-SHIFT2: br %r14
118 %res = atomicrmw umin i16 *%src, i16 %b seq_cst
122 ; Check unsigned maximum.
123 define i16 @f4(i16 *%src, i16 %b) {
125 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
126 ; CHECK: nill %r2, 65532
127 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
128 ; CHECK: [[LOOP:\.[^:]*]]:
129 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
130 ; CHECK: clrjhe [[ROT]], %r3, [[KEEP:\..*]]
131 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
133 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
134 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
136 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
139 ; CHECK-SHIFT1-LABEL: f4:
140 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
141 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
143 ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
145 ; CHECK-SHIFT1: br %r14
147 ; CHECK-SHIFT2-LABEL: f4:
148 ; CHECK-SHIFT2: sll %r3, 16
150 ; CHECK-SHIFT2: clrjhe {{%r[0-9]+}}, %r3,
153 ; CHECK-SHIFT2: br %r14
154 %res = atomicrmw umax i16 *%src, i16 %b seq_cst
158 ; Check the lowest useful signed minimum value. We need to load 0x80010000
159 ; into the source register.
160 define i16 @f5(i16 *%src) {
162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32769
163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
167 ; CHECK-SHIFT1-LABEL: f5:
168 ; CHECK-SHIFT1: br %r14
169 ; CHECK-SHIFT2-LABEL: f5:
170 ; CHECK-SHIFT2: br %r14
171 %res = atomicrmw min i16 *%src, i16 -32767 seq_cst
175 ; Check the highest useful signed maximum value. We need to load 0x7ffe0000
176 ; into the source register.
177 define i16 @f6(i16 *%src) {
179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32766
180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
184 ; CHECK-SHIFT1-LABEL: f6:
185 ; CHECK-SHIFT1: br %r14
186 ; CHECK-SHIFT2-LABEL: f6:
187 ; CHECK-SHIFT2: br %r14
188 %res = atomicrmw max i16 *%src, i16 32766 seq_cst
192 ; Check the lowest useful unsigned maximum value. We need to load 0x00010000
193 ; into the source register.
194 define i16 @f7(i16 *%src) {
196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 1
197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]],
198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
201 ; CHECK-SHIFT1-LABEL: f7:
202 ; CHECK-SHIFT1: br %r14
203 ; CHECK-SHIFT2-LABEL: f7:
204 ; CHECK-SHIFT2: br %r14
205 %res = atomicrmw umin i16 *%src, i16 1 seq_cst
209 ; Check the highest useful unsigned maximum value. We need to load 0xfffe0000
210 ; into the source register.
211 define i16 @f8(i16 *%src) {
213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65534
214 ; CHECK: clrjhe [[ROT:%r[0-9]+]], [[SRC2]],
215 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
218 ; CHECK-SHIFT1-LABEL: f8:
219 ; CHECK-SHIFT1: br %r14
220 ; CHECK-SHIFT2-LABEL: f8:
221 ; CHECK-SHIFT2: br %r14
222 %res = atomicrmw umax i16 *%src, i16 65534 seq_cst