1 ; Test 32-bit conditional stores that are presented as selects.
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
5 declare void @foo(i32 *)
7 ; Test the simple case, with the loaded value first.
8 define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
11 ; CHECK: jl [[LABEL:[^ ]*]]
13 ; CHECK: st %r3, 0(%r2)
16 %cond = icmp ult i32 %limit, 420
17 %orig = load i32 *%ptr
18 %res = select i1 %cond, i32 %orig, i32 %alt
19 store i32 %res, i32 *%ptr
23 ; ...and with the loaded value second
24 define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
27 ; CHECK: jhe [[LABEL:[^ ]*]]
29 ; CHECK: st %r3, 0(%r2)
32 %cond = icmp ult i32 %limit, 420
33 %orig = load i32 *%ptr
34 %res = select i1 %cond, i32 %alt, i32 %orig
35 store i32 %res, i32 *%ptr
39 ; Test cases where the value is explicitly sign-extended to 64 bits, with the
41 define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
44 ; CHECK: jl [[LABEL:[^ ]*]]
46 ; CHECK: st %r3, 0(%r2)
49 %cond = icmp ult i32 %limit, 420
50 %orig = load i32 *%ptr
51 %ext = sext i32 %orig to i64
52 %res = select i1 %cond, i64 %ext, i64 %alt
53 %trunc = trunc i64 %res to i32
54 store i32 %trunc, i32 *%ptr
58 ; ...and with the loaded value second
59 define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
62 ; CHECK: jhe [[LABEL:[^ ]*]]
64 ; CHECK: st %r3, 0(%r2)
67 %cond = icmp ult i32 %limit, 420
68 %orig = load i32 *%ptr
69 %ext = sext i32 %orig to i64
70 %res = select i1 %cond, i64 %alt, i64 %ext
71 %trunc = trunc i64 %res to i32
72 store i32 %trunc, i32 *%ptr
76 ; Test cases where the value is explicitly zero-extended to 32 bits, with the
78 define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
81 ; CHECK: jl [[LABEL:[^ ]*]]
83 ; CHECK: st %r3, 0(%r2)
86 %cond = icmp ult i32 %limit, 420
87 %orig = load i32 *%ptr
88 %ext = zext i32 %orig to i64
89 %res = select i1 %cond, i64 %ext, i64 %alt
90 %trunc = trunc i64 %res to i32
91 store i32 %trunc, i32 *%ptr
95 ; ...and with the loaded value second
96 define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
99 ; CHECK: jhe [[LABEL:[^ ]*]]
101 ; CHECK: st %r3, 0(%r2)
104 %cond = icmp ult i32 %limit, 420
105 %orig = load i32 *%ptr
106 %ext = zext i32 %orig to i64
107 %res = select i1 %cond, i64 %alt, i64 %ext
108 %trunc = trunc i64 %res to i32
109 store i32 %trunc, i32 *%ptr
113 ; Check the high end of the aligned ST range.
114 define void @f7(i32 *%base, i32 %alt, i32 %limit) {
117 ; CHECK: jl [[LABEL:[^ ]*]]
119 ; CHECK: st %r3, 4092(%r2)
122 %ptr = getelementptr i32 *%base, i64 1023
123 %cond = icmp ult i32 %limit, 420
124 %orig = load i32 *%ptr
125 %res = select i1 %cond, i32 %orig, i32 %alt
126 store i32 %res, i32 *%ptr
130 ; Check the next word up, which should use STY instead of ST.
131 define void @f8(i32 *%base, i32 %alt, i32 %limit) {
134 ; CHECK: jl [[LABEL:[^ ]*]]
136 ; CHECK: sty %r3, 4096(%r2)
139 %ptr = getelementptr i32 *%base, i64 1024
140 %cond = icmp ult i32 %limit, 420
141 %orig = load i32 *%ptr
142 %res = select i1 %cond, i32 %orig, i32 %alt
143 store i32 %res, i32 *%ptr
147 ; Check the high end of the aligned STY range.
148 define void @f9(i32 *%base, i32 %alt, i32 %limit) {
151 ; CHECK: jl [[LABEL:[^ ]*]]
153 ; CHECK: sty %r3, 524284(%r2)
156 %ptr = getelementptr i32 *%base, i64 131071
157 %cond = icmp ult i32 %limit, 420
158 %orig = load i32 *%ptr
159 %res = select i1 %cond, i32 %orig, i32 %alt
160 store i32 %res, i32 *%ptr
164 ; Check the next word up, which needs separate address logic.
165 ; Other sequences besides this one would be OK.
166 define void @f10(i32 *%base, i32 %alt, i32 %limit) {
169 ; CHECK: jl [[LABEL:[^ ]*]]
171 ; CHECK: agfi %r2, 524288
172 ; CHECK: st %r3, 0(%r2)
175 %ptr = getelementptr i32 *%base, i64 131072
176 %cond = icmp ult i32 %limit, 420
177 %orig = load i32 *%ptr
178 %res = select i1 %cond, i32 %orig, i32 %alt
179 store i32 %res, i32 *%ptr
183 ; Check the low end of the STY range.
184 define void @f11(i32 *%base, i32 %alt, i32 %limit) {
187 ; CHECK: jl [[LABEL:[^ ]*]]
189 ; CHECK: sty %r3, -524288(%r2)
192 %ptr = getelementptr i32 *%base, i64 -131072
193 %cond = icmp ult i32 %limit, 420
194 %orig = load i32 *%ptr
195 %res = select i1 %cond, i32 %orig, i32 %alt
196 store i32 %res, i32 *%ptr
200 ; Check the next word down, which needs separate address logic.
201 ; Other sequences besides this one would be OK.
202 define void @f12(i32 *%base, i32 %alt, i32 %limit) {
205 ; CHECK: jl [[LABEL:[^ ]*]]
207 ; CHECK: agfi %r2, -524292
208 ; CHECK: st %r3, 0(%r2)
211 %ptr = getelementptr i32 *%base, i64 -131073
212 %cond = icmp ult i32 %limit, 420
213 %orig = load i32 *%ptr
214 %res = select i1 %cond, i32 %orig, i32 %alt
215 store i32 %res, i32 *%ptr
219 ; Check that STY allows an index.
220 define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
223 ; CHECK: jl [[LABEL:[^ ]*]]
225 ; CHECK: sty %r4, 4096(%r3,%r2)
228 %add1 = add i64 %base, %index
229 %add2 = add i64 %add1, 4096
230 %ptr = inttoptr i64 %add2 to i32 *
231 %cond = icmp ult i32 %limit, 420
232 %orig = load i32 *%ptr
233 %res = select i1 %cond, i32 %orig, i32 %alt
234 store i32 %res, i32 *%ptr
238 ; Check that volatile loads are not matched.
239 define void @f14(i32 *%ptr, i32 %alt, i32 %limit) {
241 ; CHECK: l {{%r[0-5]}}, 0(%r2)
242 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
244 ; CHECK: st {{%r[0-5]}}, 0(%r2)
246 %cond = icmp ult i32 %limit, 420
247 %orig = load volatile i32 *%ptr
248 %res = select i1 %cond, i32 %orig, i32 %alt
249 store i32 %res, i32 *%ptr
253 ; ...likewise stores. In this case we should have a conditional load into %r3.
254 define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
256 ; CHECK: jhe [[LABEL:[^ ]*]]
257 ; CHECK: l %r3, 0(%r2)
259 ; CHECK: st %r3, 0(%r2)
261 %cond = icmp ult i32 %limit, 420
262 %orig = load i32 *%ptr
263 %res = select i1 %cond, i32 %orig, i32 %alt
264 store volatile i32 %res, i32 *%ptr
268 ; Check that atomic loads are not matched. The transformation is OK for
269 ; the "unordered" case tested here, but since we don't try to handle atomic
270 ; operations at all in this context, it seems better to assert that than
271 ; to restrict the test to a stronger ordering.
272 define void @f16(i32 *%ptr, i32 %alt, i32 %limit) {
273 ; FIXME: should use a normal load instead of CS.
275 ; CHECK: l {{%r[0-5]}}, 0(%r2)
276 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
278 ; CHECK: st {{%r[0-5]}}, 0(%r2)
280 %cond = icmp ult i32 %limit, 420
281 %orig = load atomic i32 *%ptr unordered, align 4
282 %res = select i1 %cond, i32 %orig, i32 %alt
283 store i32 %res, i32 *%ptr
287 ; ...likewise stores.
288 define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
289 ; FIXME: should use a normal store instead of CS.
291 ; CHECK: jhe [[LABEL:[^ ]*]]
292 ; CHECK: l %r3, 0(%r2)
294 ; CHECK: st %r3, 0(%r2)
296 %cond = icmp ult i32 %limit, 420
297 %orig = load i32 *%ptr
298 %res = select i1 %cond, i32 %orig, i32 %alt
299 store atomic i32 %res, i32 *%ptr unordered, align 4
303 ; Try a frame index base.
304 define void @f18(i32 %alt, i32 %limit) {
306 ; CHECK: brasl %r14, foo@PLT
308 ; CHECK: jl [[LABEL:[^ ]*]]
310 ; CHECK: st {{%r[0-9]+}}, {{[0-9]+}}(%r15)
312 ; CHECK: brasl %r14, foo@PLT
315 call void @foo(i32 *%ptr)
316 %cond = icmp ult i32 %limit, 420
317 %orig = load i32 *%ptr
318 %res = select i1 %cond, i32 %orig, i32 %alt
319 store i32 %res, i32 *%ptr
320 call void @foo(i32 *%ptr)