1 ; Test 128-bit addition in which the second operand is variable.
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5 ; Test register addition.
6 define void @f1(i128 *%ptr) {
11 %value = load i128 *%ptr
12 %add = add i128 %value, %value
13 store i128 %add, i128 *%ptr
17 ; Test memory addition with no offset. Making the load of %a volatile
18 ; should force the memory operand to be %b.
19 define void @f2(i128 *%aptr, i64 %addr) {
21 ; CHECK: alg {{%r[0-5]}}, 8(%r3)
22 ; CHECK: alcg {{%r[0-5]}}, 0(%r3)
24 %bptr = inttoptr i64 %addr to i128 *
25 %a = load volatile i128 *%aptr
27 %add = add i128 %a, %b
28 store i128 %add, i128 *%aptr
32 ; Test the highest aligned offset that is in range of both ALG and ALCG.
33 define void @f3(i128 *%aptr, i64 %base) {
35 ; CHECK: alg {{%r[0-5]}}, 524280(%r3)
36 ; CHECK: alcg {{%r[0-5]}}, 524272(%r3)
38 %addr = add i64 %base, 524272
39 %bptr = inttoptr i64 %addr to i128 *
40 %a = load volatile i128 *%aptr
42 %add = add i128 %a, %b
43 store i128 %add, i128 *%aptr
47 ; Test the next doubleword up, which requires separate address logic for ALG.
48 define void @f4(i128 *%aptr, i64 %base) {
50 ; CHECK: lgr [[BASE:%r[1-5]]], %r3
51 ; CHECK: agfi [[BASE]], 524288
52 ; CHECK: alg {{%r[0-5]}}, 0([[BASE]])
53 ; CHECK: alcg {{%r[0-5]}}, 524280(%r3)
55 %addr = add i64 %base, 524280
56 %bptr = inttoptr i64 %addr to i128 *
57 %a = load volatile i128 *%aptr
59 %add = add i128 %a, %b
60 store i128 %add, i128 *%aptr
64 ; Test the next doubleword after that, which requires separate logic for
65 ; both instructions. It would be better to create an anchor at 524288
66 ; that both instructions can use, but that isn't implemented yet.
67 define void @f5(i128 *%aptr, i64 %base) {
69 ; CHECK: alg {{%r[0-5]}}, 0({{%r[1-5]}})
70 ; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
72 %addr = add i64 %base, 524288
73 %bptr = inttoptr i64 %addr to i128 *
74 %a = load volatile i128 *%aptr
76 %add = add i128 %a, %b
77 store i128 %add, i128 *%aptr
81 ; Test the lowest displacement that is in range of both ALG and ALCG.
82 define void @f6(i128 *%aptr, i64 %base) {
84 ; CHECK: alg {{%r[0-5]}}, -524280(%r3)
85 ; CHECK: alcg {{%r[0-5]}}, -524288(%r3)
87 %addr = add i64 %base, -524288
88 %bptr = inttoptr i64 %addr to i128 *
89 %a = load volatile i128 *%aptr
91 %add = add i128 %a, %b
92 store i128 %add, i128 *%aptr
96 ; Test the next doubleword down, which is out of range of the ALCG.
97 define void @f7(i128 *%aptr, i64 %base) {
99 ; CHECK: alg {{%r[0-5]}}, -524288(%r3)
100 ; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
102 %addr = add i64 %base, -524296
103 %bptr = inttoptr i64 %addr to i128 *
104 %a = load volatile i128 *%aptr
105 %b = load i128 *%bptr
106 %add = add i128 %a, %b
107 store i128 %add, i128 *%aptr