1 ; Test that compares are ommitted if CC already has the right value
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
8 ; Addition provides enough for equality comparisons with zero. First teest
10 define i32 @f1(i32 %a, i32 %b, i32 *%dest) {
12 ; CHECK: afi %r2, 1000000
13 ; CHECK-NEXT: je .L{{.*}}
16 %res = add i32 %a, 1000000
17 %cmp = icmp eq i32 %res, 0
18 br i1 %cmp, label %exit, label %store
21 store i32 %b, i32 *%dest
28 ; ...and again with NE.
29 define i32 @f2(i32 %a, i32 %b, i32 *%dest) {
31 ; CHECK: afi %r2, 1000000
32 ; CHECK-NEXT: jne .L{{.*}}
35 %res = add i32 %a, 1000000
36 %cmp = icmp ne i32 %res, 0
37 br i1 %cmp, label %exit, label %store
40 store i32 %b, i32 *%dest
47 ; SLT requires a comparison.
48 define i32 @f3(i32 %a, i32 %b, i32 *%dest) {
50 ; CHECK: afi %r2, 1000000
51 ; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
54 %res = add i32 %a, 1000000
55 %cmp = icmp slt i32 %res, 0
56 br i1 %cmp, label %exit, label %store
59 store i32 %b, i32 *%dest
67 define i32 @f4(i32 %a, i32 %b, i32 *%dest) {
69 ; CHECK: afi %r2, 1000000
70 ; CHECK-NEXT: cijle %r2, 0, .L{{.*}}
73 %res = add i32 %a, 1000000
74 %cmp = icmp sle i32 %res, 0
75 br i1 %cmp, label %exit, label %store
78 store i32 %b, i32 *%dest
86 define i32 @f5(i32 %a, i32 %b, i32 *%dest) {
88 ; CHECK: afi %r2, 1000000
89 ; CHECK-NEXT: cijh %r2, 0, .L{{.*}}
92 %res = add i32 %a, 1000000
93 %cmp = icmp sgt i32 %res, 0
94 br i1 %cmp, label %exit, label %store
97 store i32 %b, i32 *%dest
105 define i32 @f6(i32 %a, i32 %b, i32 *%dest) {
107 ; CHECK: afi %r2, 1000000
108 ; CHECK-NEXT: cijhe %r2, 0, .L{{.*}}
111 %res = add i32 %a, 1000000
112 %cmp = icmp sge i32 %res, 0
113 br i1 %cmp, label %exit, label %store
116 store i32 %b, i32 *%dest
123 ; Subtraction also provides enough for equality comparisons with zero.
124 define i32 @f7(i32 %a, i32 %b, i32 *%dest) {
126 ; CHECK: s %r2, 0(%r4)
127 ; CHECK-NEXT: jne .L{{.*}}
130 %cur = load i32 *%dest
131 %res = sub i32 %a, %cur
132 %cmp = icmp ne i32 %res, 0
133 br i1 %cmp, label %exit, label %store
136 store i32 %b, i32 *%dest
143 ; ...but not for ordered comparisons.
144 define i32 @f8(i32 %a, i32 %b, i32 *%dest) {
146 ; CHECK: s %r2, 0(%r4)
147 ; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
150 %cur = load i32 *%dest
151 %res = sub i32 %a, %cur
152 %cmp = icmp slt i32 %res, 0
153 br i1 %cmp, label %exit, label %store
156 store i32 %b, i32 *%dest
163 ; Logic register-register instructions also provide enough for equality
164 ; comparisons with zero.
165 define i32 @f9(i32 %a, i32 %b, i32 *%dest) {
168 ; CHECK-NEXT: jl .L{{.*}}
171 %res = and i32 %a, %b
172 %cmp = icmp ne i32 %res, 0
173 br i1 %cmp, label %exit, label %store
176 store i32 %b, i32 *%dest
183 ; ...but not for ordered comparisons.
184 define i32 @f10(i32 %a, i32 %b, i32 *%dest) {
187 ; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
190 %res = and i32 %a, %b
191 %cmp = icmp slt i32 %res, 0
192 br i1 %cmp, label %exit, label %store
195 store i32 %b, i32 *%dest
202 ; Logic register-immediate instructions also provide enough for equality
203 ; comparisons with zero if the immediate covers the whole register.
204 define i32 @f11(i32 %a, i32 %b, i32 *%dest) {
206 ; CHECK: nilf %r2, 100
207 ; CHECK-NEXT: jl .L{{.*}}
210 %res = and i32 %a, 100
211 %cmp = icmp ne i32 %res, 0
212 br i1 %cmp, label %exit, label %store
215 store i32 %b, i32 *%dest
222 ; Partial logic register-immediate instructions do not provide simple
224 define i32 @f12(i32 %a, i32 %b, i32 *%dest) {
226 ; CHECK: nill %r2, 65436
227 ; CHECK-NEXT: cijlh %r2, 0, .L{{.*}}
230 %res = and i32 %a, -100
231 %cmp = icmp ne i32 %res, 0
232 br i1 %cmp, label %exit, label %store
235 store i32 %b, i32 *%dest
242 ; SRA provides the same CC result as a comparison with zero.
243 define i32 @f13(i32 %a, i32 %b, i32 *%dest) {
245 ; CHECK: sra %r2, 0(%r3)
246 ; CHECK-NEXT: je .L{{.*}}
249 %res = ashr i32 %a, %b
250 %cmp = icmp eq i32 %res, 0
251 br i1 %cmp, label %exit, label %store
254 store i32 %b, i32 *%dest
261 ; ...and again with NE.
262 define i32 @f14(i32 %a, i32 %b, i32 *%dest) {
264 ; CHECK: sra %r2, 0(%r3)
265 ; CHECK-NEXT: jlh .L{{.*}}
268 %res = ashr i32 %a, %b
269 %cmp = icmp ne i32 %res, 0
270 br i1 %cmp, label %exit, label %store
273 store i32 %b, i32 *%dest
281 define i32 @f15(i32 %a, i32 %b, i32 *%dest) {
283 ; CHECK: sra %r2, 0(%r3)
284 ; CHECK-NEXT: jl .L{{.*}}
287 %res = ashr i32 %a, %b
288 %cmp = icmp slt i32 %res, 0
289 br i1 %cmp, label %exit, label %store
292 store i32 %b, i32 *%dest
300 define i32 @f16(i32 %a, i32 %b, i32 *%dest) {
302 ; CHECK: sra %r2, 0(%r3)
303 ; CHECK-NEXT: jle .L{{.*}}
306 %res = ashr i32 %a, %b
307 %cmp = icmp sle i32 %res, 0
308 br i1 %cmp, label %exit, label %store
311 store i32 %b, i32 *%dest
319 define i32 @f17(i32 %a, i32 %b, i32 *%dest) {
321 ; CHECK: sra %r2, 0(%r3)
322 ; CHECK-NEXT: jh .L{{.*}}
325 %res = ashr i32 %a, %b
326 %cmp = icmp sgt i32 %res, 0
327 br i1 %cmp, label %exit, label %store
330 store i32 %b, i32 *%dest
338 define i32 @f18(i32 %a, i32 %b, i32 *%dest) {
340 ; CHECK: sra %r2, 0(%r3)
341 ; CHECK-NEXT: jhe .L{{.*}}
344 %res = ashr i32 %a, %b
345 %cmp = icmp sge i32 %res, 0
346 br i1 %cmp, label %exit, label %store
349 store i32 %b, i32 *%dest
356 ; RISBG provides the same result as a comparison against zero.
358 define i64 @f19(i64 %a, i64 %b, i64 *%dest) {
360 ; CHECK: risbg %r2, %r3, 0, 190, 0
361 ; CHECK-NEXT: je .L{{.*}}
364 %res = and i64 %b, -2
365 %cmp = icmp eq i64 %res, 0
366 br i1 %cmp, label %exit, label %store
369 store i64 %b, i64 *%dest
376 ; ...and the SLT case.
377 define i64 @f20(i64 %a, i64 %b, i64 *%dest) {
379 ; CHECK: risbg %r2, %r3, 0, 190, 0
380 ; CHECK-NEXT: jl .L{{.*}}
383 %res = and i64 %b, -2
384 %cmp = icmp slt i64 %res, 0
385 br i1 %cmp, label %exit, label %store
388 store i64 %b, i64 *%dest
395 ; Test a case where the register we're testing is set by a non-CC-clobbering
397 define i32 @f21(i32 %a, i32 %b, i32 *%dest) {
399 ; CHECK: afi %r2, 1000000
401 ; CHECK-NEXT: blah %r2
402 ; CHECK-NEXT: #NO_APP
403 ; CHECK-NEXT: cije %r2, 0, .L{{.*}}
406 %add = add i32 %a, 1000000
407 %res = call i32 asm "blah $0", "=r,0" (i32 %add)
408 %cmp = icmp eq i32 %res, 0
409 br i1 %cmp, label %exit, label %store
412 store i32 %b, i32 *%dest
419 ; ...and again with a CC-clobbering instruction.
420 define i32 @f22(i32 %a, i32 %b, i32 *%dest) {
422 ; CHECK: afi %r2, 1000000
424 ; CHECK-NEXT: blah %r2
425 ; CHECK-NEXT: #NO_APP
426 ; CHECK-NEXT: cije %r2, 0, .L{{.*}}
429 %add = add i32 %a, 1000000
430 %res = call i32 asm "blah $0", "=r,0,~{cc}" (i32 %add)
431 %cmp = icmp eq i32 %res, 0
432 br i1 %cmp, label %exit, label %store
435 store i32 %b, i32 *%dest
442 ; Check that stores do not interfere.
443 define i32 @f23(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) {
445 ; CHECK: afi %r2, 1000000
446 ; CHECK-NEXT: st %r2, 0(%r4)
447 ; CHECK-NEXT: jne .L{{.*}}
450 %res = add i32 %a, 1000000
451 store i32 %res, i32 *%dest1
452 %cmp = icmp ne i32 %res, 0
453 br i1 %cmp, label %exit, label %store
456 store i32 %b, i32 *%dest2
463 ; Check that calls do interfere.
464 define void @f24(i32 *%ptr) {
466 ; CHECK: afi [[REG:%r[0-9]+]], 1000000
467 ; CHECK-NEXT: brasl %r14, foo@PLT
468 ; CHECK-NEXT: cijlh [[REG]], 0, .L{{.*}}
471 %val = load i32 *%ptr
472 %xor = xor i32 %val, 1
473 %add = add i32 %xor, 1000000
475 %cmp = icmp ne i32 %add, 0
476 br i1 %cmp, label %exit, label %store
479 store i32 %add, i32 *%ptr
486 ; Check that inline asms don't interfere if they don't clobber CC.
487 define void @f25(i32 %a, i32 *%ptr) {
489 ; CHECK: afi %r2, 1000000
492 ; CHECK-NEXT: #NO_APP
493 ; CHECK-NEXT: jne .L{{.*}}
496 %add = add i32 %a, 1000000
497 call void asm sideeffect "blah", "r"(i32 %add)
498 %cmp = icmp ne i32 %add, 0
499 br i1 %cmp, label %exit, label %store
502 store i32 %add, i32 *%ptr
509 ; ...but do interfere if they do clobber CC.
510 define void @f26(i32 %a, i32 *%ptr) {
512 ; CHECK: afi %r2, 1000000
515 ; CHECK-NEXT: #NO_APP
516 ; CHECK-NEXT: cijlh %r2, 0, .L{{.*}}
519 %add = add i32 %a, 1000000
520 call void asm sideeffect "blah", "r,~{cc}"(i32 %add)
521 %cmp = icmp ne i32 %add, 0
522 br i1 %cmp, label %exit, label %store
525 store i32 %add, i32 *%ptr
532 ; Test a case where CC is set based on a different register from the
534 define i32 @f27(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) {
536 ; CHECK: afi %r2, 1000000
537 ; CHECK-NEXT: sr %r3, %r2
538 ; CHECK-NEXT: st %r3, 0(%r4)
539 ; CHECK-NEXT: cije %r2, 0, .L{{.*}}
542 %add = add i32 %a, 1000000
543 %sub = sub i32 %b, %add
544 store i32 %sub, i32 *%dest1
545 %cmp = icmp eq i32 %add, 0
546 br i1 %cmp, label %exit, label %store
549 store i32 %sub, i32 *%dest2
556 ; Make sure that we don't confuse a base register for a destination.
557 define void @f28(i64 %a, i64 *%dest) {
559 ; CHECK: xi 0(%r2), 15
560 ; CHECK: cgije %r2, 0, .L{{.*}}
563 %ptr = inttoptr i64 %a to i8 *
565 %xor = xor i8 %val, 15
566 store i8 %xor, i8 *%ptr
567 %cmp = icmp eq i64 %a, 0
568 br i1 %cmp, label %exit, label %store
571 store i64 %a, i64 *%dest