1 ; Testg 64-bit signed division and remainder.
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5 ; Testg register division. The result is in the second of the two registers.
6 define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
8 ; CHECK-NOT: {{%r[234]}}
10 ; CHECK: stg %r3, 0(%r5)
12 %div = sdiv i64 %a, %b
13 store i64 %div, i64 *%dest
17 ; Testg register remainder. The result is in the first of the two registers.
18 define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
20 ; CHECK-NOT: {{%r[234]}}
21 ; CHECK: dsgr %r2, %r4
22 ; CHECK: stg %r2, 0(%r5)
24 %rem = srem i64 %a, %b
25 store i64 %rem, i64 *%dest
29 ; Testg that division and remainder use a single instruction.
30 define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
32 ; CHECK-NOT: {{%r[234]}}
33 ; CHECK: dsgr %r2, %r4
37 %div = sdiv i64 %a, %b
38 %rem = srem i64 %a, %b
39 %or = or i64 %rem, %div
43 ; Testg memory division with no displacement.
44 define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
46 ; CHECK-NOT: {{%r[234]}}
47 ; CHECK: dsg %r2, 0(%r4)
48 ; CHECK: stg %r3, 0(%r5)
51 %div = sdiv i64 %a, %b
52 store i64 %div, i64 *%dest
56 ; Testg memory remainder with no displacement.
57 define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
59 ; CHECK-NOT: {{%r[234]}}
60 ; CHECK: dsg %r2, 0(%r4)
61 ; CHECK: stg %r2, 0(%r5)
64 %rem = srem i64 %a, %b
65 store i64 %rem, i64 *%dest
69 ; Testg both memory division and memory remainder.
70 define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
72 ; CHECK-NOT: {{%r[234]}}
73 ; CHECK: dsg %r2, 0(%r4)
74 ; CHECK-NOT: {{dsg|dsgr}}
78 %div = sdiv i64 %a, %b
79 %rem = srem i64 %a, %b
80 %or = or i64 %rem, %div
84 ; Check the high end of the DSG range.
85 define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
87 ; CHECK: dsg %r2, 524280(%r4)
89 %ptr = getelementptr i64 *%src, i64 65535
91 %rem = srem i64 %a, %b
95 ; Check the next doubleword up, which needs separate address logic.
96 ; Other sequences besides this one would be OK.
97 define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
99 ; CHECK: agfi %r4, 524288
100 ; CHECK: dsg %r2, 0(%r4)
102 %ptr = getelementptr i64 *%src, i64 65536
104 %rem = srem i64 %a, %b
108 ; Check the high end of the negative aligned DSG range.
109 define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
111 ; CHECK: dsg %r2, -8(%r4)
113 %ptr = getelementptr i64 *%src, i64 -1
115 %rem = srem i64 %a, %b
119 ; Check the low end of the DSG range.
120 define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
122 ; CHECK: dsg %r2, -524288(%r4)
124 %ptr = getelementptr i64 *%src, i64 -65536
126 %rem = srem i64 %a, %b
130 ; Check the next doubleword down, which needs separate address logic.
131 ; Other sequences besides this one would be OK.
132 define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
134 ; CHECK: agfi %r4, -524296
135 ; CHECK: dsg %r2, 0(%r4)
137 %ptr = getelementptr i64 *%src, i64 -65537
139 %rem = srem i64 %a, %b
143 ; Check that DSG allows an index.
144 define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
146 ; CHECK: dsg %r2, 524287(%r5,%r4)
148 %add1 = add i64 %src, %index
149 %add2 = add i64 %add1, 524287
150 %ptr = inttoptr i64 %add2 to i64 *
152 %rem = srem i64 %a, %b