1 ; Test vector subtraction.
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
5 ; Test a v16i8 subtraction.
6 define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
8 ; CHECK: vsb %v24, %v26, %v28
10 %ret = sub <16 x i8> %val1, %val2
14 ; Test a v8i16 subtraction.
15 define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
17 ; CHECK: vsh %v24, %v26, %v28
19 %ret = sub <8 x i16> %val1, %val2
23 ; Test a v4i32 subtraction.
24 define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
26 ; CHECK: vsf %v24, %v26, %v28
28 %ret = sub <4 x i32> %val1, %val2
32 ; Test a v2i64 subtraction.
33 define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
35 ; CHECK: vsg %v24, %v26, %v28
37 %ret = sub <2 x i64> %val1, %val2
41 ; Test a v4f32 subtraction, as an example of an operation that needs to be
42 ; scalarized and reassembled. At present there's an unnecessary move that
43 ; could be avoided with smarter ordering. It also isn't important whether
44 ; the VSLDBs use the result of the VLRs or use %v24 and %v26 directly.
45 define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
47 ; CHECK-DAG: vlr %v[[A1:[0-5]]], %v24
48 ; CHECK-DAG: vlr %v[[A2:[0-5]]], %v26
49 ; CHECK-DAG: vrepf %v[[B1:[0-5]]], %v[[A1]], 1
50 ; CHECK-DAG: vrepf %v[[B2:[0-5]]], %v[[A2]], 1
51 ; CHECK-DAG: vrepf %v[[C1:[0-5]]], %v[[A1]], 2
52 ; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v[[A2]], 2
53 ; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v[[A1]], 3
54 ; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v[[A2]], 3
55 ; CHECK-DAG: ler %f[[A1copy:[0-5]]], %f[[A1]]
56 ; CHECK-DAG: sebr %f[[A1copy]], %f[[A2]]
57 ; CHECK-DAG: sebr %f[[B1]], %f[[B2]]
58 ; CHECK-DAG: sebr %f[[C1]], %f[[C2]]
59 ; CHECK-DAG: sebr %f[[D1]], %f[[D2]]
60 ; CHECK-DAG: vmrhf [[HIGH:%v[0-9]+]], %v[[A1copy]], %v[[B1]]
61 ; CHECK-DAG: vmrhf [[LOW:%v[0-9]+]], %v[[C1]], %v[[D1]]
62 ; CHECK: vmrhg %v24, [[HIGH]], [[LOW]]
64 %ret = fsub <4 x float> %val1, %val2
68 ; Test a v2f64 subtraction.
69 define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1,
72 ; CHECK: vfsdb %v24, %v26, %v28
74 %ret = fsub <2 x double> %val1, %val2
78 ; Test an f64 subtraction that uses vector registers.
79 define double @f7(<2 x double> %val1, <2 x double> %val2) {
81 ; CHECK: wfsdb %f0, %v24, %v26
83 %scalar1 = extractelement <2 x double> %val1, i32 0
84 %scalar2 = extractelement <2 x double> %val2, i32 0
85 %ret = fsub double %scalar1, %scalar2