1 ; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 | FileCheck %s
3 define i64 @f1(i64 %a, i64 %b) {
6 ; CHECK: subs r0, r0, r2
12 define i64 @f2(i64 %a, i64 %b) {
15 ; CHECK: adds r0, r0, r0
17 ; CHECK: subs r0, r0, r2
20 %tmp2 = sub i64 %tmp1, %b
25 define i64 @f3(i32 %vi) {
28 ; CHECK: movw [[REG:r[0-9]+]], #36102
29 ; CHECK: sbcs r{{[0-9]+}}, [[REG]]
30 %v0 = zext i32 %vi to i64
31 %v1 = xor i64 %v0, -155057456198619
32 %v4 = add i64 %v1, 155057456198619
33 %v5 = add i64 %v4, %v1