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HEAD
Expand vector bswap in LegalizeVectorOps
[oota-llvm.git]
/
test
/
CodeGen
/
Thumb2
/
mul_const.ll
1
; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 | FileCheck %s
2
; rdar://7069502
3
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define i32 @t1(i32 %v) nounwind readnone {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: add.w r0, r0, r0, lsl #3
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%0 = mul i32 %v, 9
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ret i32 %0
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}
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define i32 @t2(i32 %v) nounwind readnone {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: rsb r0, r0, r0, lsl #3
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%0 = mul i32 %v, 7
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ret i32 %0
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}