1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -asm-verbose=false | FileCheck %s -check-prefix=64BIT
4 ; In 32-bit the partial register stall would degrade performance.
6 define zeroext i16 @t1(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
9 ; 32BIT: movw 20(%esp), %ax
10 ; 32BIT-NOT: movw %ax, %cx
11 ; 32BIT: leal 1(%eax), %ecx
14 ; 64BIT-NOT: movw %si, %ax
15 ; 64BIT: leal 1(%rsi), %eax
16 %0 = icmp eq i16 %k, %c ; <i1> [#uses=1]
17 %1 = add i16 %k, 1 ; <i16> [#uses=3]
18 br i1 %0, label %bb, label %bb1
21 tail call void @foo(i16 zeroext %1) nounwind
28 define zeroext i16 @t2(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
31 ; 32BIT: movw 20(%esp), %ax
32 ; 32BIT-NOT: movw %ax, %cx
33 ; 32BIT: leal -1(%eax), %ecx
36 ; 64BIT-NOT: movw %si, %ax
39 %0 = icmp eq i16 %k, %c ; <i1> [#uses=1]
40 %1 = add i16 %k, -1 ; <i16> [#uses=3]
41 br i1 %0, label %bb, label %bb1
44 tail call void @foo(i16 zeroext %1) nounwind
51 declare void @foo(i16 zeroext)
53 define zeroext i16 @t3(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
56 ; 32BIT: movw 20(%esp), %ax
57 ; 32BIT-NOT: movw %ax, %cx
58 ; 32BIT: leal 2(%eax), %ecx
61 ; 64BIT-NOT: movw %si, %ax
62 ; 64BIT: addl $2, %eax
63 %0 = add i16 %k, 2 ; <i16> [#uses=3]
64 %1 = icmp eq i16 %k, %c ; <i1> [#uses=1]
65 br i1 %1, label %bb, label %bb1
68 tail call void @foo(i16 zeroext %0) nounwind
75 define zeroext i16 @t4(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
78 ; 32BIT: movw 16(%esp), %ax
79 ; 32BIT: movw 20(%esp), %cx
80 ; 32BIT-NOT: movw %cx, %dx
81 ; 32BIT: leal (%ecx,%eax), %edx
84 ; 64BIT-NOT: movw %si, %ax
85 ; 64BIT: addl %edi, %eax
86 %0 = add i16 %k, %c ; <i16> [#uses=3]
87 %1 = icmp eq i16 %k, %c ; <i1> [#uses=1]
88 br i1 %1, label %bb, label %bb1
91 tail call void @foo(i16 zeroext %0) nounwind