1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -disable-fp-elim | FileCheck %s
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim | FileCheck --check-prefix=SSE %s
3 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -disable-fp-elim | FileCheck --check-prefix=AVX %s
6 ; Stackmap Header: no constants - 6 callsites
7 ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
8 ; CHECK-NEXT: __LLVM_StackMaps:
12 ; CHECK-NEXT: .short 0
20 ; Functions and stack size
21 ; CHECK-NEXT: .quad _test
23 ; CHECK-NEXT: .quad _property_access1
25 ; CHECK-NEXT: .quad _property_access2
26 ; CHECK-NEXT: .quad 24
27 ; CHECK-NEXT: .quad _property_access3
28 ; CHECK-NEXT: .quad 24
29 ; CHECK-NEXT: .quad _anyreg_test1
30 ; CHECK-NEXT: .quad 56
31 ; CHECK-NEXT: .quad _anyreg_test2
32 ; CHECK-NEXT: .quad 56
33 ; CHECK-NEXT: .quad _patchpoint_spilldef
34 ; CHECK-NEXT: .quad 56
35 ; CHECK-NEXT: .quad _patchpoint_spillargs
36 ; CHECK-NEXT: .quad 88
42 ; CHECK-LABEL: .long L{{.*}}-_test
43 ; CHECK-NEXT: .short 0
45 ; CHECK-NEXT: .short 3
49 ; CHECK-NEXT: .short {{[0-9]+}}
54 ; CHECK-NEXT: .short {{[0-9]+}}
59 ; CHECK-NEXT: .short 0
61 define i64 @test() nounwind ssp uwtable {
63 call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 15, i8* null, i32 2, i32 1, i32 2, i64 3)
67 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
68 ; CHECK-LABEL: .long L{{.*}}-_property_access1
69 ; CHECK-NEXT: .short 0
71 ; CHECK-NEXT: .short 2
72 ; Loc 0: Register <-- this is the return register
75 ; CHECK-NEXT: .short {{[0-9]+}}
80 ; CHECK-NEXT: .short {{[0-9]+}}
82 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
84 %f = inttoptr i64 12297829382473034410 to i8*
85 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 15, i8* %f, i32 1, i8* %obj)
89 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
90 ; CHECK-LABEL: .long L{{.*}}-_property_access2
91 ; CHECK-NEXT: .short 0
93 ; CHECK-NEXT: .short 2
94 ; Loc 0: Register <-- this is the return register
97 ; CHECK-NEXT: .short {{[0-9]+}}
100 ; CHECK-NEXT: .byte 1
101 ; CHECK-NEXT: .byte 8
102 ; CHECK-NEXT: .short {{[0-9]+}}
103 ; CHECK-NEXT: .long 0
104 define i64 @property_access2() nounwind ssp uwtable {
106 %obj = alloca i64, align 8
107 %f = inttoptr i64 12297829382473034410 to i8*
108 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %f, i32 1, i64* %obj)
112 ; property access 3 - %obj is a frame index
113 ; CHECK-LABEL: .long L{{.*}}-_property_access3
114 ; CHECK-NEXT: .short 0
116 ; CHECK-NEXT: .short 2
117 ; Loc 0: Register <-- this is the return register
118 ; CHECK-NEXT: .byte 1
119 ; CHECK-NEXT: .byte 8
120 ; CHECK-NEXT: .short {{[0-9]+}}
121 ; CHECK-NEXT: .long 0
122 ; Loc 1: Direct RBP - ofs
123 ; CHECK-NEXT: .byte 2
124 ; CHECK-NEXT: .byte 8
125 ; CHECK-NEXT: .short 6
127 define i64 @property_access3() nounwind ssp uwtable {
129 %obj = alloca i64, align 8
130 %f = inttoptr i64 12297829382473034410 to i8*
131 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 15, i8* %f, i32 0, i64* %obj)
136 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
137 ; CHECK-NEXT: .short 0
139 ; CHECK-NEXT: .short 14
140 ; Loc 0: Register <-- this is the return register
141 ; CHECK-NEXT: .byte 1
142 ; CHECK-NEXT: .byte 8
143 ; CHECK-NEXT: .short {{[0-9]+}}
144 ; CHECK-NEXT: .long 0
146 ; CHECK-NEXT: .byte 1
147 ; CHECK-NEXT: .byte 8
148 ; CHECK-NEXT: .short {{[0-9]+}}
149 ; CHECK-NEXT: .long 0
151 ; CHECK-NEXT: .byte 1
152 ; CHECK-NEXT: .byte 8
153 ; CHECK-NEXT: .short {{[0-9]+}}
154 ; CHECK-NEXT: .long 0
156 ; CHECK-NEXT: .byte 1
157 ; CHECK-NEXT: .byte 8
158 ; CHECK-NEXT: .short {{[0-9]+}}
159 ; CHECK-NEXT: .long 0
161 ; CHECK-NEXT: .byte 1
162 ; CHECK-NEXT: .byte 8
163 ; CHECK-NEXT: .short {{[0-9]+}}
164 ; CHECK-NEXT: .long 0
166 ; CHECK-NEXT: .byte 1
167 ; CHECK-NEXT: .byte 8
168 ; CHECK-NEXT: .short {{[0-9]+}}
169 ; CHECK-NEXT: .long 0
171 ; CHECK-NEXT: .byte 1
172 ; CHECK-NEXT: .byte 8
173 ; CHECK-NEXT: .short {{[0-9]+}}
174 ; CHECK-NEXT: .long 0
176 ; CHECK-NEXT: .byte 1
177 ; CHECK-NEXT: .byte 8
178 ; CHECK-NEXT: .short {{[0-9]+}}
179 ; CHECK-NEXT: .long 0
181 ; CHECK-NEXT: .byte 1
182 ; CHECK-NEXT: .byte 8
183 ; CHECK-NEXT: .short {{[0-9]+}}
184 ; CHECK-NEXT: .long 0
186 ; CHECK-NEXT: .byte 1
187 ; CHECK-NEXT: .byte 8
188 ; CHECK-NEXT: .short {{[0-9]+}}
189 ; CHECK-NEXT: .long 0
191 ; CHECK-NEXT: .byte 1
192 ; CHECK-NEXT: .byte 8
193 ; CHECK-NEXT: .short {{[0-9]+}}
194 ; CHECK-NEXT: .long 0
196 ; CHECK-NEXT: .byte 1
197 ; CHECK-NEXT: .byte 8
198 ; CHECK-NEXT: .short {{[0-9]+}}
199 ; CHECK-NEXT: .long 0
201 ; CHECK-NEXT: .byte 1
202 ; CHECK-NEXT: .byte 8
203 ; CHECK-NEXT: .short {{[0-9]+}}
204 ; CHECK-NEXT: .long 0
206 ; CHECK-NEXT: .byte 1
207 ; CHECK-NEXT: .byte 8
208 ; CHECK-NEXT: .short {{[0-9]+}}
209 ; CHECK-NEXT: .long 0
210 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
212 %f = inttoptr i64 12297829382473034410 to i8*
213 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 15, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
218 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
219 ; CHECK-NEXT: .short 0
221 ; CHECK-NEXT: .short 14
222 ; Loc 0: Register <-- this is the return register
223 ; CHECK-NEXT: .byte 1
224 ; CHECK-NEXT: .byte 8
225 ; CHECK-NEXT: .short {{[0-9]+}}
226 ; CHECK-NEXT: .long 0
228 ; CHECK-NEXT: .byte 1
229 ; CHECK-NEXT: .byte 8
230 ; CHECK-NEXT: .short {{[0-9]+}}
231 ; CHECK-NEXT: .long 0
233 ; CHECK-NEXT: .byte 1
234 ; CHECK-NEXT: .byte 8
235 ; CHECK-NEXT: .short {{[0-9]+}}
236 ; CHECK-NEXT: .long 0
238 ; CHECK-NEXT: .byte 1
239 ; CHECK-NEXT: .byte 8
240 ; CHECK-NEXT: .short {{[0-9]+}}
241 ; CHECK-NEXT: .long 0
243 ; CHECK-NEXT: .byte 1
244 ; CHECK-NEXT: .byte 8
245 ; CHECK-NEXT: .short {{[0-9]+}}
246 ; CHECK-NEXT: .long 0
248 ; CHECK-NEXT: .byte 1
249 ; CHECK-NEXT: .byte 8
250 ; CHECK-NEXT: .short {{[0-9]+}}
251 ; CHECK-NEXT: .long 0
253 ; CHECK-NEXT: .byte 1
254 ; CHECK-NEXT: .byte 8
255 ; CHECK-NEXT: .short {{[0-9]+}}
256 ; CHECK-NEXT: .long 0
258 ; CHECK-NEXT: .byte 1
259 ; CHECK-NEXT: .byte 8
260 ; CHECK-NEXT: .short {{[0-9]+}}
261 ; CHECK-NEXT: .long 0
263 ; CHECK-NEXT: .byte 1
264 ; CHECK-NEXT: .byte 8
265 ; CHECK-NEXT: .short {{[0-9]+}}
266 ; CHECK-NEXT: .long 0
268 ; CHECK-NEXT: .byte 1
269 ; CHECK-NEXT: .byte 8
270 ; CHECK-NEXT: .short {{[0-9]+}}
271 ; CHECK-NEXT: .long 0
273 ; CHECK-NEXT: .byte 1
274 ; CHECK-NEXT: .byte 8
275 ; CHECK-NEXT: .short {{[0-9]+}}
276 ; CHECK-NEXT: .long 0
278 ; CHECK-NEXT: .byte 1
279 ; CHECK-NEXT: .byte 8
280 ; CHECK-NEXT: .short {{[0-9]+}}
281 ; CHECK-NEXT: .long 0
283 ; CHECK-NEXT: .byte 1
284 ; CHECK-NEXT: .byte 8
285 ; CHECK-NEXT: .short {{[0-9]+}}
286 ; CHECK-NEXT: .long 0
288 ; CHECK-NEXT: .byte 1
289 ; CHECK-NEXT: .byte 8
290 ; CHECK-NEXT: .short {{[0-9]+}}
291 ; CHECK-NEXT: .long 0
292 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
294 %f = inttoptr i64 12297829382473034410 to i8*
295 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
299 ; Test spilling the return value of an anyregcc call.
301 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
303 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
304 ; CHECK-NEXT: .short 0
305 ; CHECK-NEXT: .short 3
306 ; Loc 0: Register (some register that will be spilled to the stack)
307 ; CHECK-NEXT: .byte 1
308 ; CHECK-NEXT: .byte 8
309 ; CHECK-NEXT: .short {{[0-9]+}}
310 ; CHECK-NEXT: .long 0
311 ; Loc 1: Register RDI
312 ; CHECK-NEXT: .byte 1
313 ; CHECK-NEXT: .byte 8
314 ; CHECK-NEXT: .short 5
315 ; CHECK-NEXT: .long 0
316 ; Loc 1: Register RSI
317 ; CHECK-NEXT: .byte 1
318 ; CHECK-NEXT: .byte 8
319 ; CHECK-NEXT: .short 4
320 ; CHECK-NEXT: .long 0
321 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
323 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
324 tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
328 ; Test spilling the arguments of an anyregcc call.
330 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
332 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
333 ; CHECK-NEXT: .short 0
334 ; CHECK-NEXT: .short 5
335 ; Loc 0: Return a register
336 ; CHECK-NEXT: .byte 1
337 ; CHECK-NEXT: .byte 8
338 ; CHECK-NEXT: .short {{[0-9]+}}
339 ; CHECK-NEXT: .long 0
340 ; Loc 1: Arg0 in a Register
341 ; CHECK-NEXT: .byte 1
342 ; CHECK-NEXT: .byte 8
343 ; CHECK-NEXT: .short {{[0-9]+}}
344 ; CHECK-NEXT: .long 0
345 ; Loc 2: Arg1 in a Register
346 ; CHECK-NEXT: .byte 1
347 ; CHECK-NEXT: .byte 8
348 ; CHECK-NEXT: .short {{[0-9]+}}
349 ; CHECK-NEXT: .long 0
350 ; Loc 3: Arg2 spilled to RBP +
351 ; CHECK-NEXT: .byte 3
352 ; CHECK-NEXT: .byte 8
353 ; CHECK-NEXT: .short 6
355 ; Loc 4: Arg3 spilled to RBP +
356 ; CHECK-NEXT: .byte 3
357 ; CHECK-NEXT: .byte 8
358 ; CHECK-NEXT: .short 6
360 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
362 tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
363 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
367 ; Make sure all regs are spilled
368 define anyregcc void @anyregcc1() {
370 ;SSE-LABEL: anyregcc1
387 ;SSE-NEXT: movaps %xmm14
388 ;SSE-NEXT: movaps %xmm13
389 ;SSE-NEXT: movaps %xmm12
390 ;SSE-NEXT: movaps %xmm11
391 ;SSE-NEXT: movaps %xmm10
392 ;SSE-NEXT: movaps %xmm9
393 ;SSE-NEXT: movaps %xmm8
394 ;SSE-NEXT: movaps %xmm7
395 ;SSE-NEXT: movaps %xmm6
396 ;SSE-NEXT: movaps %xmm5
397 ;SSE-NEXT: movaps %xmm4
398 ;SSE-NEXT: movaps %xmm3
399 ;SSE-NEXT: movaps %xmm2
400 ;SSE-NEXT: movaps %xmm1
401 ;SSE-NEXT: movaps %xmm0
419 ;AVX-NEXT: vmovaps %ymm14
420 ;AVX-NEXT: vmovaps %ymm13
421 ;AVX-NEXT: vmovaps %ymm12
422 ;AVX-NEXT: vmovaps %ymm11
423 ;AVX-NEXT: vmovaps %ymm10
424 ;AVX-NEXT: vmovaps %ymm9
425 ;AVX-NEXT: vmovaps %ymm8
426 ;AVX-NEXT: vmovaps %ymm7
427 ;AVX-NEXT: vmovaps %ymm6
428 ;AVX-NEXT: vmovaps %ymm5
429 ;AVX-NEXT: vmovaps %ymm4
430 ;AVX-NEXT: vmovaps %ymm3
431 ;AVX-NEXT: vmovaps %ymm2
432 ;AVX-NEXT: vmovaps %ymm1
433 ;AVX-NEXT: vmovaps %ymm0
434 call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{rbp},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15}"()
438 ; Make sure we don't spill any XMMs/YMMs
439 declare anyregcc void @foo()
440 define void @anyregcc2() {
442 ;SSE-LABEL: anyregcc2
443 ;SSE-NOT: movaps %xmm
444 ;AVX-LABEL: anyregcc2
445 ;AVX-NOT: vmovups %ymm
446 %a0 = call <2 x double> asm sideeffect "", "={xmm0}"() nounwind
447 %a1 = call <2 x double> asm sideeffect "", "={xmm1}"() nounwind
448 %a2 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
449 %a3 = call <2 x double> asm sideeffect "", "={xmm3}"() nounwind
450 %a4 = call <2 x double> asm sideeffect "", "={xmm4}"() nounwind
451 %a5 = call <2 x double> asm sideeffect "", "={xmm5}"() nounwind
452 %a6 = call <2 x double> asm sideeffect "", "={xmm6}"() nounwind
453 %a7 = call <2 x double> asm sideeffect "", "={xmm7}"() nounwind
454 %a8 = call <2 x double> asm sideeffect "", "={xmm8}"() nounwind
455 %a9 = call <2 x double> asm sideeffect "", "={xmm9}"() nounwind
456 %a10 = call <2 x double> asm sideeffect "", "={xmm10}"() nounwind
457 %a11 = call <2 x double> asm sideeffect "", "={xmm11}"() nounwind
458 %a12 = call <2 x double> asm sideeffect "", "={xmm12}"() nounwind
459 %a13 = call <2 x double> asm sideeffect "", "={xmm13}"() nounwind
460 %a14 = call <2 x double> asm sideeffect "", "={xmm14}"() nounwind
461 %a15 = call <2 x double> asm sideeffect "", "={xmm15}"() nounwind
462 call anyregcc void @foo()
463 call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},{xmm8},{xmm9},{xmm10},{xmm11},{xmm12},{xmm13},{xmm14},{xmm15}"(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3, <2 x double> %a4, <2 x double> %a5, <2 x double> %a6, <2 x double> %a7, <2 x double> %a8, <2 x double> %a9, <2 x double> %a10, <2 x double> %a11, <2 x double> %a12, <2 x double> %a13, <2 x double> %a14, <2 x double> %a15)
467 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
468 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)