1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -disable-fp-elim | FileCheck %s
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7 | FileCheck --check-prefix=SSE %s
3 ; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck --check-prefix=AVX %s
6 ; Stackmap Header: no constants - 6 callsites
7 ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
8 ; CHECK-NEXT: __LLVM_StackMaps:
17 ; CHECK-LABEL: .long L{{.*}}-_test
18 ; CHECK-NEXT: .short 0
20 ; CHECK-NEXT: .short 3
24 ; CHECK-NEXT: .short {{[0-9]+}}
29 ; CHECK-NEXT: .short {{[0-9]+}}
34 ; CHECK-NEXT: .short 0
36 define i64 @test() nounwind ssp uwtable {
38 call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 15, i8* null, i32 2, i32 1, i32 2, i64 3)
42 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
43 ; CHECK-LABEL: .long L{{.*}}-_property_access1
44 ; CHECK-NEXT: .short 0
46 ; CHECK-NEXT: .short 2
47 ; Loc 0: Register <-- this is the return register
50 ; CHECK-NEXT: .short {{[0-9]+}}
55 ; CHECK-NEXT: .short {{[0-9]+}}
57 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
59 %f = inttoptr i64 12297829382473034410 to i8*
60 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 15, i8* %f, i32 1, i8* %obj)
64 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
65 ; CHECK-LABEL: .long L{{.*}}-_property_access2
66 ; CHECK-NEXT: .short 0
68 ; CHECK-NEXT: .short 2
69 ; Loc 0: Register <-- this is the return register
72 ; CHECK-NEXT: .short {{[0-9]+}}
77 ; CHECK-NEXT: .short {{[0-9]+}}
79 define i64 @property_access2() nounwind ssp uwtable {
81 %obj = alloca i64, align 8
82 %f = inttoptr i64 12297829382473034410 to i8*
83 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %f, i32 1, i64* %obj)
87 ; property access 3 - %obj is a frame index
88 ; CHECK-LABEL: .long L{{.*}}-_property_access3
89 ; CHECK-NEXT: .short 0
91 ; CHECK-NEXT: .short 2
92 ; Loc 0: Register <-- this is the return register
95 ; CHECK-NEXT: .short {{[0-9]+}}
97 ; Loc 1: Direct RBP - ofs
100 ; CHECK-NEXT: .short 6
102 define i64 @property_access3() nounwind ssp uwtable {
104 %obj = alloca i64, align 8
105 %f = inttoptr i64 12297829382473034410 to i8*
106 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 15, i8* %f, i32 0, i64* %obj)
111 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
112 ; CHECK-NEXT: .short 0
114 ; CHECK-NEXT: .short 14
115 ; Loc 0: Register <-- this is the return register
116 ; CHECK-NEXT: .byte 1
117 ; CHECK-NEXT: .byte 8
118 ; CHECK-NEXT: .short {{[0-9]+}}
119 ; CHECK-NEXT: .long 0
121 ; CHECK-NEXT: .byte 1
122 ; CHECK-NEXT: .byte 8
123 ; CHECK-NEXT: .short {{[0-9]+}}
124 ; CHECK-NEXT: .long 0
126 ; CHECK-NEXT: .byte 1
127 ; CHECK-NEXT: .byte 8
128 ; CHECK-NEXT: .short {{[0-9]+}}
129 ; CHECK-NEXT: .long 0
131 ; CHECK-NEXT: .byte 1
132 ; CHECK-NEXT: .byte 8
133 ; CHECK-NEXT: .short {{[0-9]+}}
134 ; CHECK-NEXT: .long 0
136 ; CHECK-NEXT: .byte 1
137 ; CHECK-NEXT: .byte 8
138 ; CHECK-NEXT: .short {{[0-9]+}}
139 ; CHECK-NEXT: .long 0
141 ; CHECK-NEXT: .byte 1
142 ; CHECK-NEXT: .byte 8
143 ; CHECK-NEXT: .short {{[0-9]+}}
144 ; CHECK-NEXT: .long 0
146 ; CHECK-NEXT: .byte 1
147 ; CHECK-NEXT: .byte 8
148 ; CHECK-NEXT: .short {{[0-9]+}}
149 ; CHECK-NEXT: .long 0
151 ; CHECK-NEXT: .byte 1
152 ; CHECK-NEXT: .byte 8
153 ; CHECK-NEXT: .short {{[0-9]+}}
154 ; CHECK-NEXT: .long 0
156 ; CHECK-NEXT: .byte 1
157 ; CHECK-NEXT: .byte 8
158 ; CHECK-NEXT: .short {{[0-9]+}}
159 ; CHECK-NEXT: .long 0
161 ; CHECK-NEXT: .byte 1
162 ; CHECK-NEXT: .byte 8
163 ; CHECK-NEXT: .short {{[0-9]+}}
164 ; CHECK-NEXT: .long 0
166 ; CHECK-NEXT: .byte 1
167 ; CHECK-NEXT: .byte 8
168 ; CHECK-NEXT: .short {{[0-9]+}}
169 ; CHECK-NEXT: .long 0
171 ; CHECK-NEXT: .byte 1
172 ; CHECK-NEXT: .byte 8
173 ; CHECK-NEXT: .short {{[0-9]+}}
174 ; CHECK-NEXT: .long 0
176 ; CHECK-NEXT: .byte 1
177 ; CHECK-NEXT: .byte 8
178 ; CHECK-NEXT: .short {{[0-9]+}}
179 ; CHECK-NEXT: .long 0
181 ; CHECK-NEXT: .byte 1
182 ; CHECK-NEXT: .byte 8
183 ; CHECK-NEXT: .short {{[0-9]+}}
184 ; CHECK-NEXT: .long 0
185 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
187 %f = inttoptr i64 12297829382473034410 to i8*
188 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 15, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
193 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
194 ; CHECK-NEXT: .short 0
196 ; CHECK-NEXT: .short 14
197 ; Loc 0: Register <-- this is the return register
198 ; CHECK-NEXT: .byte 1
199 ; CHECK-NEXT: .byte 8
200 ; CHECK-NEXT: .short {{[0-9]+}}
201 ; CHECK-NEXT: .long 0
203 ; CHECK-NEXT: .byte 1
204 ; CHECK-NEXT: .byte 8
205 ; CHECK-NEXT: .short {{[0-9]+}}
206 ; CHECK-NEXT: .long 0
208 ; CHECK-NEXT: .byte 1
209 ; CHECK-NEXT: .byte 8
210 ; CHECK-NEXT: .short {{[0-9]+}}
211 ; CHECK-NEXT: .long 0
213 ; CHECK-NEXT: .byte 1
214 ; CHECK-NEXT: .byte 8
215 ; CHECK-NEXT: .short {{[0-9]+}}
216 ; CHECK-NEXT: .long 0
218 ; CHECK-NEXT: .byte 1
219 ; CHECK-NEXT: .byte 8
220 ; CHECK-NEXT: .short {{[0-9]+}}
221 ; CHECK-NEXT: .long 0
223 ; CHECK-NEXT: .byte 1
224 ; CHECK-NEXT: .byte 8
225 ; CHECK-NEXT: .short {{[0-9]+}}
226 ; CHECK-NEXT: .long 0
228 ; CHECK-NEXT: .byte 1
229 ; CHECK-NEXT: .byte 8
230 ; CHECK-NEXT: .short {{[0-9]+}}
231 ; CHECK-NEXT: .long 0
233 ; CHECK-NEXT: .byte 1
234 ; CHECK-NEXT: .byte 8
235 ; CHECK-NEXT: .short {{[0-9]+}}
236 ; CHECK-NEXT: .long 0
238 ; CHECK-NEXT: .byte 1
239 ; CHECK-NEXT: .byte 8
240 ; CHECK-NEXT: .short {{[0-9]+}}
241 ; CHECK-NEXT: .long 0
243 ; CHECK-NEXT: .byte 1
244 ; CHECK-NEXT: .byte 8
245 ; CHECK-NEXT: .short {{[0-9]+}}
246 ; CHECK-NEXT: .long 0
248 ; CHECK-NEXT: .byte 1
249 ; CHECK-NEXT: .byte 8
250 ; CHECK-NEXT: .short {{[0-9]+}}
251 ; CHECK-NEXT: .long 0
253 ; CHECK-NEXT: .byte 1
254 ; CHECK-NEXT: .byte 8
255 ; CHECK-NEXT: .short {{[0-9]+}}
256 ; CHECK-NEXT: .long 0
258 ; CHECK-NEXT: .byte 1
259 ; CHECK-NEXT: .byte 8
260 ; CHECK-NEXT: .short {{[0-9]+}}
261 ; CHECK-NEXT: .long 0
263 ; CHECK-NEXT: .byte 1
264 ; CHECK-NEXT: .byte 8
265 ; CHECK-NEXT: .short {{[0-9]+}}
266 ; CHECK-NEXT: .long 0
267 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
269 %f = inttoptr i64 12297829382473034410 to i8*
270 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
274 ; Test spilling the return value of an anyregcc call.
276 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
278 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
279 ; CHECK-NEXT: .short 0
280 ; CHECK-NEXT: .short 3
281 ; Loc 0: Register (some register that will be spilled to the stack)
282 ; CHECK-NEXT: .byte 1
283 ; CHECK-NEXT: .byte 8
284 ; CHECK-NEXT: .short {{[0-9]+}}
285 ; CHECK-NEXT: .long 0
286 ; Loc 1: Register RDI
287 ; CHECK-NEXT: .byte 1
288 ; CHECK-NEXT: .byte 8
289 ; CHECK-NEXT: .short 5
290 ; CHECK-NEXT: .long 0
291 ; Loc 1: Register RSI
292 ; CHECK-NEXT: .byte 1
293 ; CHECK-NEXT: .byte 8
294 ; CHECK-NEXT: .short 4
295 ; CHECK-NEXT: .long 0
296 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
298 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
299 tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
303 ; Test spilling the arguments of an anyregcc call.
305 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
307 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
308 ; CHECK-NEXT: .short 0
309 ; CHECK-NEXT: .short 5
310 ; Loc 0: Return a register
311 ; CHECK-NEXT: .byte 1
312 ; CHECK-NEXT: .byte 8
313 ; CHECK-NEXT: .short {{[0-9]+}}
314 ; CHECK-NEXT: .long 0
315 ; Loc 1: Arg0 in a Register
316 ; CHECK-NEXT: .byte 1
317 ; CHECK-NEXT: .byte 8
318 ; CHECK-NEXT: .short {{[0-9]+}}
319 ; CHECK-NEXT: .long 0
320 ; Loc 2: Arg1 in a Register
321 ; CHECK-NEXT: .byte 1
322 ; CHECK-NEXT: .byte 8
323 ; CHECK-NEXT: .short {{[0-9]+}}
324 ; CHECK-NEXT: .long 0
325 ; Loc 3: Arg2 spilled to RBP +
326 ; CHECK-NEXT: .byte 3
327 ; CHECK-NEXT: .byte 8
328 ; CHECK-NEXT: .short 6
330 ; Loc 4: Arg3 spilled to RBP +
331 ; CHECK-NEXT: .byte 3
332 ; CHECK-NEXT: .byte 8
333 ; CHECK-NEXT: .short 6
335 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
337 tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
338 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
342 ; Make sure all regs are spilled
343 define anyregcc void @anyregcc1() {
345 ;SSE-LABEL: anyregcc1
362 ;SSE-NEXT: movaps %xmm14
363 ;SSE-NEXT: movaps %xmm13
364 ;SSE-NEXT: movaps %xmm12
365 ;SSE-NEXT: movaps %xmm11
366 ;SSE-NEXT: movaps %xmm10
367 ;SSE-NEXT: movaps %xmm9
368 ;SSE-NEXT: movaps %xmm8
369 ;SSE-NEXT: movaps %xmm7
370 ;SSE-NEXT: movaps %xmm6
371 ;SSE-NEXT: movaps %xmm5
372 ;SSE-NEXT: movaps %xmm4
373 ;SSE-NEXT: movaps %xmm3
374 ;SSE-NEXT: movaps %xmm2
375 ;SSE-NEXT: movaps %xmm1
376 ;SSE-NEXT: movaps %xmm0
394 ;AVX-NEXT: vmovups %ymm14
395 ;AVX-NEXT: vmovups %ymm13
396 ;AVX-NEXT: vmovups %ymm12
397 ;AVX-NEXT: vmovups %ymm11
398 ;AVX-NEXT: vmovups %ymm10
399 ;AVX-NEXT: vmovups %ymm9
400 ;AVX-NEXT: vmovups %ymm8
401 ;AVX-NEXT: vmovups %ymm7
402 ;AVX-NEXT: vmovups %ymm6
403 ;AVX-NEXT: vmovups %ymm5
404 ;AVX-NEXT: vmovups %ymm4
405 ;AVX-NEXT: vmovups %ymm3
406 ;AVX-NEXT: vmovups %ymm2
407 ;AVX-NEXT: vmovups %ymm1
408 ;AVX-NEXT: vmovups %ymm0
409 call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{rbp},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15}"()
413 ; Make sure we don't spill any XMMs/YMMs
414 declare anyregcc void @foo()
415 define void @anyregcc2() {
417 ;SSE-LABEL: anyregcc2
418 ;SSE-NOT: movaps %xmm
419 ;AVX-LABEL: anyregcc2
420 ;AVX-NOT: vmovups %ymm
421 %a0 = call <2 x double> asm sideeffect "", "={xmm0}"() nounwind
422 %a1 = call <2 x double> asm sideeffect "", "={xmm1}"() nounwind
423 %a2 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
424 %a3 = call <2 x double> asm sideeffect "", "={xmm3}"() nounwind
425 %a4 = call <2 x double> asm sideeffect "", "={xmm4}"() nounwind
426 %a5 = call <2 x double> asm sideeffect "", "={xmm5}"() nounwind
427 %a6 = call <2 x double> asm sideeffect "", "={xmm6}"() nounwind
428 %a7 = call <2 x double> asm sideeffect "", "={xmm7}"() nounwind
429 %a8 = call <2 x double> asm sideeffect "", "={xmm8}"() nounwind
430 %a9 = call <2 x double> asm sideeffect "", "={xmm9}"() nounwind
431 %a10 = call <2 x double> asm sideeffect "", "={xmm10}"() nounwind
432 %a11 = call <2 x double> asm sideeffect "", "={xmm11}"() nounwind
433 %a12 = call <2 x double> asm sideeffect "", "={xmm12}"() nounwind
434 %a13 = call <2 x double> asm sideeffect "", "={xmm13}"() nounwind
435 %a14 = call <2 x double> asm sideeffect "", "={xmm14}"() nounwind
436 %a15 = call <2 x double> asm sideeffect "", "={xmm15}"() nounwind
437 call anyregcc void @foo()
438 call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},{xmm8},{xmm9},{xmm10},{xmm11},{xmm12},{xmm13},{xmm14},{xmm15}"(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3, <2 x double> %a4, <2 x double> %a5, <2 x double> %a6, <2 x double> %a7, <2 x double> %a8, <2 x double> %a9, <2 x double> %a10, <2 x double> %a11, <2 x double> %a12, <2 x double> %a13, <2 x double> %a14, <2 x double> %a15)
442 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
443 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)