1 ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
5 define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
6 ; CHECK-LABEL: val_compare_and_swap:
7 ; CHECK: movq %rsi, %rax
8 ; CHECK: movq %rcx, %rbx
9 ; CHECK: movq %r8, %rcx
11 ; CHECK: cmpxchg16b (%rdi)
13 %pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire
14 %val = extractvalue { i128, i1 } %pair, 0
18 define void @fetch_and_nand(i128* %p, i128 %bits) {
19 ; CHECK-LABEL: fetch_and_nand:
20 ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
21 ; CHECK-DAG: movq (%rdi), %rax
22 ; CHECK-DAG: movq 8(%rdi), %rdx
24 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
25 ; CHECK: movq %rdx, %rcx
26 ; CHECK: andq [[INCHI]], %rcx
27 ; CHECK: movq %rax, %rbx
28 ; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
29 ; CHECK: andq %rsi, %rbx
33 ; CHECK: cmpxchg16b (%rdi)
36 ; CHECK: movq %rax, _var
37 ; CHECK: movq %rdx, _var+8
38 %val = atomicrmw nand i128* %p, i128 %bits release
39 store i128 %val, i128* @var, align 16
43 define void @fetch_and_or(i128* %p, i128 %bits) {
44 ; CHECK-LABEL: fetch_and_or:
45 ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
46 ; CHECK-DAG: movq (%rdi), %rax
47 ; CHECK-DAG: movq 8(%rdi), %rdx
49 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
50 ; CHECK: movq %rax, %rbx
51 ; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
52 ; CHECK: orq %rsi, %rbx
53 ; CHECK: movq %rdx, %rcx
54 ; CHECK: orq [[INCHI]], %rcx
56 ; CHECK: cmpxchg16b (%rdi)
59 ; CHECK: movq %rax, _var
60 ; CHECK: movq %rdx, _var+8
62 %val = atomicrmw or i128* %p, i128 %bits seq_cst
63 store i128 %val, i128* @var, align 16
67 define void @fetch_and_add(i128* %p, i128 %bits) {
68 ; CHECK-LABEL: fetch_and_add:
69 ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
70 ; CHECK-DAG: movq (%rdi), %rax
71 ; CHECK-DAG: movq 8(%rdi), %rdx
73 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
74 ; CHECK: movq %rax, %rbx
75 ; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
76 ; CHECK: addq %rsi, %rbx
77 ; CHECK: movq %rdx, %rcx
78 ; CHECK: adcq [[INCHI]], %rcx
80 ; CHECK: cmpxchg16b (%rdi)
83 ; CHECK: movq %rax, _var
84 ; CHECK: movq %rdx, _var+8
86 %val = atomicrmw add i128* %p, i128 %bits seq_cst
87 store i128 %val, i128* @var, align 16
91 define void @fetch_and_sub(i128* %p, i128 %bits) {
92 ; CHECK-LABEL: fetch_and_sub:
93 ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
94 ; CHECK-DAG: movq (%rdi), %rax
95 ; CHECK-DAG: movq 8(%rdi), %rdx
97 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
98 ; CHECK: movq %rax, %rbx
99 ; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
100 ; CHECK: subq %rsi, %rbx
101 ; CHECK: movq %rdx, %rcx
102 ; CHECK: sbbq [[INCHI]], %rcx
104 ; CHECK: cmpxchg16b (%rdi)
105 ; CHECK: jne [[LOOP]]
107 ; CHECK: movq %rax, _var
108 ; CHECK: movq %rdx, _var+8
110 %val = atomicrmw sub i128* %p, i128 %bits seq_cst
111 store i128 %val, i128* @var, align 16
115 define void @fetch_and_min(i128* %p, i128 %bits) {
116 ; CHECK-LABEL: fetch_and_min:
117 ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
118 ; CHECK-DAG: movq (%rdi), %rax
119 ; CHECK-DAG: movq 8(%rdi), %rdx
121 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
125 ; CHECK: cmovneq %rax, %rbx
126 ; CHECK: movq [[INCHI]], %rcx
127 ; CHECK: cmovneq %rdx, %rcx
129 ; CHECK: cmpxchg16b (%rdi)
130 ; CHECK: jne [[LOOP]]
132 ; CHECK: movq %rax, _var
133 ; CHECK: movq %rdx, _var+8
135 %val = atomicrmw min i128* %p, i128 %bits seq_cst
136 store i128 %val, i128* @var, align 16
140 define void @fetch_and_max(i128* %p, i128 %bits) {
141 ; CHECK-LABEL: fetch_and_max:
142 ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
143 ; CHECK-DAG: movq (%rdi), %rax
144 ; CHECK-DAG: movq 8(%rdi), %rdx
146 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
150 ; CHECK: cmovneq %rax, %rbx
151 ; CHECK: movq [[INCHI]], %rcx
152 ; CHECK: cmovneq %rdx, %rcx
154 ; CHECK: cmpxchg16b (%rdi)
155 ; CHECK: jne [[LOOP]]
157 ; CHECK: movq %rax, _var
158 ; CHECK: movq %rdx, _var+8
160 %val = atomicrmw max i128* %p, i128 %bits seq_cst
161 store i128 %val, i128* @var, align 16
165 define void @fetch_and_umin(i128* %p, i128 %bits) {
166 ; CHECK-LABEL: fetch_and_umin:
167 ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
168 ; CHECK-DAG: movq (%rdi), %rax
169 ; CHECK-DAG: movq 8(%rdi), %rdx
171 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
175 ; CHECK: cmovneq %rax, %rbx
176 ; CHECK: movq [[INCHI]], %rcx
177 ; CHECK: cmovneq %rdx, %rcx
179 ; CHECK: cmpxchg16b (%rdi)
180 ; CHECK: jne [[LOOP]]
182 ; CHECK: movq %rax, _var
183 ; CHECK: movq %rdx, _var+8
185 %val = atomicrmw umin i128* %p, i128 %bits seq_cst
186 store i128 %val, i128* @var, align 16
190 define void @fetch_and_umax(i128* %p, i128 %bits) {
191 ; CHECK-LABEL: fetch_and_umax:
192 ; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
193 ; CHECK-DAG: movq (%rdi), %rax
194 ; CHECK-DAG: movq 8(%rdi), %rdx
196 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
200 ; CHECK: cmovneq %rax, %rbx
201 ; CHECK: movq [[INCHI]], %rcx
202 ; CHECK: cmovneq %rdx, %rcx
204 ; CHECK: cmpxchg16b (%rdi)
205 ; CHECK: jne [[LOOP]]
207 ; CHECK: movq %rax, _var
208 ; CHECK: movq %rdx, _var+8
210 %val = atomicrmw umax i128* %p, i128 %bits seq_cst
211 store i128 %val, i128* @var, align 16
215 define i128 @atomic_load_seq_cst(i128* %p) {
216 ; CHECK-LABEL: atomic_load_seq_cst:
217 ; CHECK: xorl %eax, %eax
218 ; CHECK: xorl %edx, %edx
219 ; CHECK: xorl %ebx, %ebx
220 ; CHECK: xorl %ecx, %ecx
222 ; CHECK: cmpxchg16b (%rdi)
224 %r = load atomic i128, i128* %p seq_cst, align 16
228 define i128 @atomic_load_relaxed(i128* %p) {
229 ; CHECK: atomic_load_relaxed:
230 ; CHECK: xorl %eax, %eax
231 ; CHECK: xorl %edx, %edx
232 ; CHECK: xorl %ebx, %ebx
233 ; CHECK: xorl %ecx, %ecx
235 ; CHECK: cmpxchg16b (%rdi)
237 %r = load atomic i128, i128* %p monotonic, align 16
241 define void @atomic_store_seq_cst(i128* %p, i128 %in) {
242 ; CHECK-LABEL: atomic_store_seq_cst:
243 ; CHECK: movq %rdx, %rcx
244 ; CHECK: movq %rsi, %rbx
245 ; CHECK: movq (%rdi), %rax
246 ; CHECK: movq 8(%rdi), %rdx
248 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
250 ; CHECK: cmpxchg16b (%rdi)
251 ; CHECK: jne [[LOOP]]
252 ; CHECK-NOT: callq ___sync_lock_test_and_set_16
254 store atomic i128 %in, i128* %p seq_cst, align 16
258 define void @atomic_store_release(i128* %p, i128 %in) {
259 ; CHECK-LABEL: atomic_store_release:
260 ; CHECK: movq %rdx, %rcx
261 ; CHECK: movq %rsi, %rbx
262 ; CHECK: movq (%rdi), %rax
263 ; CHECK: movq 8(%rdi), %rdx
265 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
267 ; CHECK: cmpxchg16b (%rdi)
268 ; CHECK: jne [[LOOP]]
270 store atomic i128 %in, i128* %p release, align 16
274 define void @atomic_store_relaxed(i128* %p, i128 %in) {
275 ; CHECK-LABEL: atomic_store_relaxed:
276 ; CHECK: movq %rdx, %rcx
277 ; CHECK: movq %rsi, %rbx
278 ; CHECK: movq (%rdi), %rax
279 ; CHECK: movq 8(%rdi), %rdx
281 ; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
283 ; CHECK: cmpxchg16b (%rdi)
284 ; CHECK: jne [[LOOP]]
286 store atomic i128 %in, i128* %p unordered, align 16