1 ; RUN: llc < %s -march=x86-64 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=X64
2 ; RUN: llc < %s -march=x86 -mattr=+sse2 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=X32
4 ; On x86, an atomic rmw operation that does not modify the value in memory
5 ; (such as atomic add 0) can be replaced by an mfence followed by a mov.
6 ; This is explained (with the motivation for such an optimization) in
7 ; http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
9 define i8 @add8(i8* %p) {
13 %1 = atomicrmw add i8* %p, i8 0 monotonic
17 define i16 @or16(i16* %p) {
21 %1 = atomicrmw or i16* %p, i16 0 acquire
25 define i32 @xor32(i32* %p) {
29 %1 = atomicrmw xor i32* %p, i32 0 release
33 define i64 @sub64(i64* %p) {
38 %1 = atomicrmw sub i64* %p, i64 0 seq_cst
42 define i128 @or128(i128* %p) {
45 %1 = atomicrmw or i128* %p, i128 0 monotonic
49 ; For 'and', the idempotent value is (-1)
50 define i32 @and32 (i32* %p) {
54 %1 = atomicrmw and i32* %p, i32 -1 acq_rel