1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7-avx | FileCheck %s
3 ; We don't check any vinsertf128 variant with immediate 0 because that's just a blend.
5 define <4 x double> @test_x86_avx_vinsertf128_pd_256_1(<4 x double> %a0, <2 x double> %a1) {
6 ; CHECK-LABEL: test_x86_avx_vinsertf128_pd_256_1:
7 ; CHECK: vinsertf128 $1, %xmm1, %ymm0, %ymm0
8 %res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %a0, <2 x double> %a1, i8 1)
11 declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
13 define <8 x float> @test_x86_avx_vinsertf128_ps_256_1(<8 x float> %a0, <4 x float> %a1) {
14 ; CHECK-LABEL: test_x86_avx_vinsertf128_ps_256_1:
15 ; CHECK: vinsertf128 $1, %xmm1, %ymm0, %ymm0
16 %res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %a0, <4 x float> %a1, i8 1)
19 declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone
21 define <8 x i32> @test_x86_avx_vinsertf128_si_256_1(<8 x i32> %a0, <4 x i32> %a1) {
22 ; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_1:
23 ; CHECK: vinsertf128 $1, %xmm1, %ymm0, %ymm0
24 %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 1)
28 ; Verify that high bits of the immediate are masked off. This should be the equivalent
29 ; of a vinsertf128 $0 which should be optimized into a blend, so just check that it's
30 ; not a vinsertf128 $1.
31 define <8 x i32> @test_x86_avx_vinsertf128_si_256_2(<8 x i32> %a0, <4 x i32> %a1) {
32 ; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_2:
33 ; CHECK-NOT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
34 %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 2)
37 declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone
39 ; We don't check any vextractf128 variant with immediate 0 because that's just a move.
41 define <2 x double> @test_x86_avx_vextractf128_pd_256_1(<4 x double> %a0) {
42 ; CHECK-LABEL: test_x86_avx_vextractf128_pd_256_1:
43 ; CHECK: vextractf128 $1, %ymm0, %xmm0
44 %res = call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a0, i8 1)
47 declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
49 define <4 x float> @test_x86_avx_vextractf128_ps_256_1(<8 x float> %a0) {
50 ; CHECK-LABEL: test_x86_avx_vextractf128_ps_256_1:
51 ; CHECK: vextractf128 $1, %ymm0, %xmm0
52 %res = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a0, i8 1)
55 declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
57 define <4 x i32> @test_x86_avx_vextractf128_si_256_1(<8 x i32> %a0) {
58 ; CHECK-LABEL: test_x86_avx_vextractf128_si_256_1:
59 ; CHECK: vextractf128 $1, %ymm0, %xmm0
60 %res = call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %a0, i8 1)
63 declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
65 ; Verify that high bits of the immediate are masked off. This should be the equivalent
66 ; of a vextractf128 $0 which should be optimized away, so just check that it's
67 ; not a vextractf128 of any kind.
68 define <2 x double> @test_x86_avx_extractf128_pd_256_2(<4 x double> %a0) {
69 ; CHECK-LABEL: test_x86_avx_extractf128_pd_256_2:
70 ; CHECK-NOT: vextractf128
71 %res = call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a0, i8 2)
76 define <4 x double> @test_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
77 ; CHECK-LABEL: test_x86_avx_blend_pd_256:
79 %res = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 7) ; <<4 x double>> [#uses=1]
82 declare <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double>, <4 x double>, i32) nounwind readnone
85 define <8 x float> @test_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
86 ; CHECK-LABEL: test_x86_avx_blend_ps_256:
88 %res = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 7) ; <<8 x float>> [#uses=1]
91 declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i32) nounwind readnone
94 define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) {
95 ; CHECK-LABEL: test_x86_avx_dp_ps_256:
97 %res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i32 7) ; <<8 x float>> [#uses=1]
100 declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i32) nounwind readnone
103 define <2 x i64> @test_x86_sse2_psll_dq(<2 x i64> %a0) {
104 ; CHECK-LABEL: test_x86_sse2_psll_dq:
105 ; CHECK: vpslldq {{.*#+}} xmm0 = zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]
106 %res = call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
109 declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone
112 define <2 x i64> @test_x86_sse2_psrl_dq(<2 x i64> %a0) {
113 ; CHECK-LABEL: test_x86_sse2_psrl_dq:
114 ; CHECK: vpsrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
115 %res = call <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
118 declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) nounwind readnone
121 define <2 x double> @test_x86_sse41_blendpd(<2 x double> %a0, <2 x double> %a1) {
122 ; CHECK-LABEL: test_x86_sse41_blendpd:
124 %res = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i8 2) ; <<2 x double>> [#uses=1]
125 ret <2 x double> %res
127 declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nounwind readnone
130 define <4 x float> @test_x86_sse41_blendps(<4 x float> %a0, <4 x float> %a1) {
131 ; CHECK-LABEL: test_x86_sse41_blendps:
133 %res = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
136 declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone
139 define <8 x i16> @test_x86_sse41_pblendw(<8 x i16> %a0, <8 x i16> %a1) {
140 ; CHECK-LABEL: test_x86_sse41_pblendw:
142 %res = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i8 7) ; <<8 x i16>> [#uses=1]
145 declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone
148 define <4 x i32> @test_x86_sse41_pmovsxbd(<16 x i8> %a0) {
149 ; CHECK-LABEL: test_x86_sse41_pmovsxbd:
151 ; CHECK-NEXT: vpmovsxbd %xmm0, %xmm0
153 %res = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1]
156 declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
159 define <2 x i64> @test_x86_sse41_pmovsxbq(<16 x i8> %a0) {
160 ; CHECK-LABEL: test_x86_sse41_pmovsxbq:
162 ; CHECK-NEXT: vpmovsxbq %xmm0, %xmm0
164 %res = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1]
167 declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone
170 define <8 x i16> @test_x86_sse41_pmovsxbw(<16 x i8> %a0) {
171 ; CHECK-LABEL: test_x86_sse41_pmovsxbw:
173 ; CHECK-NEXT: vpmovsxbw %xmm0, %xmm0
175 %res = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1]
178 declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone
181 define <2 x i64> @test_x86_sse41_pmovsxdq(<4 x i32> %a0) {
182 ; CHECK-LABEL: test_x86_sse41_pmovsxdq:
184 ; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0
186 %res = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1]
189 declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone
192 define <4 x i32> @test_x86_sse41_pmovsxwd(<8 x i16> %a0) {
193 ; CHECK-LABEL: test_x86_sse41_pmovsxwd:
195 ; CHECK-NEXT: vpmovsxwd %xmm0, %xmm0
197 %res = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1]
200 declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
203 define <2 x i64> @test_x86_sse41_pmovsxwq(<8 x i16> %a0) {
204 ; CHECK-LABEL: test_x86_sse41_pmovsxwq:
206 ; CHECK-NEXT: vpmovsxwq %xmm0, %xmm0
208 %res = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1]
211 declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone