1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mattr=avx,aes,pclmul | FileCheck %s
4 define <2 x i64> @test_x86_aesni_aesdec(<2 x i64> %a0, <2 x i64> %a1) {
5 ; CHECK-LABEL: test_x86_aesni_aesdec:
7 ; CHECK-NEXT: vaesdec %xmm1, %xmm0, %xmm0
9 %res = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
12 declare <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64>, <2 x i64>) nounwind readnone
15 define <2 x i64> @test_x86_aesni_aesdeclast(<2 x i64> %a0, <2 x i64> %a1) {
16 ; CHECK-LABEL: test_x86_aesni_aesdeclast:
18 ; CHECK-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0
20 %res = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
23 declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>) nounwind readnone
26 define <2 x i64> @test_x86_aesni_aesenc(<2 x i64> %a0, <2 x i64> %a1) {
27 ; CHECK-LABEL: test_x86_aesni_aesenc:
29 ; CHECK-NEXT: vaesenc %xmm1, %xmm0, %xmm0
31 %res = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
34 declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>) nounwind readnone
37 define <2 x i64> @test_x86_aesni_aesenclast(<2 x i64> %a0, <2 x i64> %a1) {
38 ; CHECK-LABEL: test_x86_aesni_aesenclast:
40 ; CHECK-NEXT: vaesenclast %xmm1, %xmm0, %xmm0
42 %res = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
45 declare <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64>, <2 x i64>) nounwind readnone
48 define <2 x i64> @test_x86_aesni_aesimc(<2 x i64> %a0) {
49 ; CHECK-LABEL: test_x86_aesni_aesimc:
51 ; CHECK-NEXT: vaesimc %xmm0, %xmm0
53 %res = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %a0) ; <<2 x i64>> [#uses=1]
56 declare <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64>) nounwind readnone
59 define <2 x i64> @test_x86_aesni_aeskeygenassist(<2 x i64> %a0) {
60 ; CHECK-LABEL: test_x86_aesni_aeskeygenassist:
62 ; CHECK-NEXT: vaeskeygenassist $7, %xmm0, %xmm0
64 %res = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %a0, i8 7) ; <<2 x i64>> [#uses=1]
67 declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8) nounwind readnone
70 define <2 x double> @test_x86_sse2_add_sd(<2 x double> %a0, <2 x double> %a1) {
71 ; CHECK-LABEL: test_x86_sse2_add_sd:
73 ; CHECK-NEXT: vaddsd %xmm1, %xmm0, %xmm0
75 %res = call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
78 declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) nounwind readnone
81 define <2 x double> @test_x86_sse2_cmp_pd(<2 x double> %a0, <2 x double> %a1) {
82 ; CHECK-LABEL: test_x86_sse2_cmp_pd:
84 ; CHECK-NEXT: vcmpordpd %xmm1, %xmm0, %xmm0
86 %res = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
89 declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounwind readnone
92 define <2 x double> @test_x86_sse2_cmp_sd(<2 x double> %a0, <2 x double> %a1) {
93 ; CHECK-LABEL: test_x86_sse2_cmp_sd:
95 ; CHECK-NEXT: vcmpordsd %xmm1, %xmm0, %xmm0
97 %res = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
100 declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone
103 define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) {
104 ; CHECK-LABEL: test_x86_sse2_comieq_sd:
106 ; CHECK-NEXT: vcomisd %xmm1, %xmm0
107 ; CHECK-NEXT: sete %al
108 ; CHECK-NEXT: movzbl %al, %eax
110 %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
113 declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
116 define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) {
117 ; CHECK-LABEL: test_x86_sse2_comige_sd:
119 ; CHECK-NEXT: vcomisd %xmm1, %xmm0
120 ; CHECK-NEXT: setae %al
121 ; CHECK-NEXT: movzbl %al, %eax
123 %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
126 declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readnone
129 define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) {
130 ; CHECK-LABEL: test_x86_sse2_comigt_sd:
132 ; CHECK-NEXT: vcomisd %xmm1, %xmm0
133 ; CHECK-NEXT: seta %al
134 ; CHECK-NEXT: movzbl %al, %eax
136 %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
139 declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>) nounwind readnone
142 define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) {
143 ; CHECK-LABEL: test_x86_sse2_comile_sd:
145 ; CHECK-NEXT: vcomisd %xmm1, %xmm0
146 ; CHECK-NEXT: setbe %al
147 ; CHECK-NEXT: movzbl %al, %eax
149 %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
152 declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>) nounwind readnone
155 define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) {
156 ; CHECK-LABEL: test_x86_sse2_comilt_sd:
158 ; CHECK-NEXT: vcomisd %xmm1, %xmm0
159 ; CHECK-NEXT: sbbl %eax, %eax
160 ; CHECK-NEXT: andl $1, %eax
162 %res = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
165 declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readnone
168 define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) {
169 ; CHECK-LABEL: test_x86_sse2_comineq_sd:
171 ; CHECK-NEXT: vcomisd %xmm1, %xmm0
172 ; CHECK-NEXT: setne %al
173 ; CHECK-NEXT: movzbl %al, %eax
175 %res = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
178 declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>) nounwind readnone
181 define <2 x double> @test_x86_sse2_cvtdq2pd(<4 x i32> %a0) {
182 ; CHECK-LABEL: test_x86_sse2_cvtdq2pd:
184 ; CHECK-NEXT: vcvtdq2pd %xmm0, %xmm0
186 %res = call <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32> %a0) ; <<2 x double>> [#uses=1]
187 ret <2 x double> %res
189 declare <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32>) nounwind readnone
192 define <4 x float> @test_x86_sse2_cvtdq2ps(<4 x i32> %a0) {
193 ; CHECK-LABEL: test_x86_sse2_cvtdq2ps:
195 ; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
197 %res = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %a0) ; <<4 x float>> [#uses=1]
200 declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
203 define <4 x i32> @test_x86_sse2_cvtpd2dq(<2 x double> %a0) {
204 ; CHECK-LABEL: test_x86_sse2_cvtpd2dq:
206 ; CHECK-NEXT: vcvtpd2dq %xmm0, %xmm0
208 %res = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1]
211 declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) nounwind readnone
214 define <4 x float> @test_x86_sse2_cvtpd2ps(<2 x double> %a0) {
215 ; CHECK-LABEL: test_x86_sse2_cvtpd2ps:
217 ; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm0
219 %res = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0) ; <<4 x float>> [#uses=1]
222 declare <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double>) nounwind readnone
225 define <4 x i32> @test_x86_sse2_cvtps2dq(<4 x float> %a0) {
226 ; CHECK-LABEL: test_x86_sse2_cvtps2dq:
228 ; CHECK-NEXT: vcvtps2dq %xmm0, %xmm0
230 %res = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]
233 declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) nounwind readnone
236 define <2 x double> @test_x86_sse2_cvtps2pd(<4 x float> %a0) {
237 ; CHECK-LABEL: test_x86_sse2_cvtps2pd:
239 ; CHECK-NEXT: vcvtps2pd %xmm0, %xmm0
241 %res = call <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float> %a0) ; <<2 x double>> [#uses=1]
242 ret <2 x double> %res
244 declare <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float>) nounwind readnone
247 define i32 @test_x86_sse2_cvtsd2si(<2 x double> %a0) {
248 ; CHECK-LABEL: test_x86_sse2_cvtsd2si:
250 ; CHECK-NEXT: vcvtsd2si %xmm0, %eax
252 %res = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a0) ; <i32> [#uses=1]
255 declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone
258 define <4 x float> @test_x86_sse2_cvtsd2ss(<4 x float> %a0, <2 x double> %a1) {
259 ; CHECK-LABEL: test_x86_sse2_cvtsd2ss:
261 ; CHECK-NEXT: vcvtsd2ss %xmm1, %xmm0, %xmm0
263 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]
266 declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone
269 define <2 x double> @test_x86_sse2_cvtsi2sd(<2 x double> %a0) {
270 ; CHECK-LABEL: test_x86_sse2_cvtsi2sd:
272 ; CHECK-NEXT: movl $7, %eax
273 ; CHECK-NEXT: vcvtsi2sdl %eax, %xmm0, %xmm0
275 %res = call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> %a0, i32 7) ; <<2 x double>> [#uses=1]
276 ret <2 x double> %res
278 declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind readnone
281 define <2 x double> @test_x86_sse2_cvtss2sd(<2 x double> %a0, <4 x float> %a1) {
282 ; CHECK-LABEL: test_x86_sse2_cvtss2sd:
284 ; CHECK-NEXT: vcvtss2sd %xmm1, %xmm0, %xmm0
286 %res = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> %a0, <4 x float> %a1) ; <<2 x double>> [#uses=1]
287 ret <2 x double> %res
289 declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind readnone
292 define <4 x i32> @test_x86_sse2_cvttpd2dq(<2 x double> %a0) {
293 ; CHECK-LABEL: test_x86_sse2_cvttpd2dq:
295 ; CHECK-NEXT: vcvttpd2dq %xmm0, %xmm0
297 %res = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1]
300 declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind readnone
303 define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) {
304 ; CHECK-LABEL: test_x86_sse2_cvttps2dq:
306 ; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
308 %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]
311 declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone
314 define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) {
315 ; CHECK-LABEL: test_x86_sse2_cvttsd2si:
317 ; CHECK-NEXT: vcvttsd2si %xmm0, %eax
319 %res = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0) ; <i32> [#uses=1]
322 declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone
325 define <2 x double> @test_x86_sse2_div_sd(<2 x double> %a0, <2 x double> %a1) {
326 ; CHECK-LABEL: test_x86_sse2_div_sd:
328 ; CHECK-NEXT: vdivsd %xmm1, %xmm0, %xmm0
330 %res = call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
331 ret <2 x double> %res
333 declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) nounwind readnone
337 define <2 x double> @test_x86_sse2_max_pd(<2 x double> %a0, <2 x double> %a1) {
338 ; CHECK-LABEL: test_x86_sse2_max_pd:
340 ; CHECK-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
342 %res = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
343 ret <2 x double> %res
345 declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone
348 define <2 x double> @test_x86_sse2_max_sd(<2 x double> %a0, <2 x double> %a1) {
349 ; CHECK-LABEL: test_x86_sse2_max_sd:
351 ; CHECK-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
353 %res = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
354 ret <2 x double> %res
356 declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone
359 define <2 x double> @test_x86_sse2_min_pd(<2 x double> %a0, <2 x double> %a1) {
360 ; CHECK-LABEL: test_x86_sse2_min_pd:
362 ; CHECK-NEXT: vminpd %xmm1, %xmm0, %xmm0
364 %res = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
365 ret <2 x double> %res
367 declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
370 define <2 x double> @test_x86_sse2_min_sd(<2 x double> %a0, <2 x double> %a1) {
371 ; CHECK-LABEL: test_x86_sse2_min_sd:
373 ; CHECK-NEXT: vminsd %xmm1, %xmm0, %xmm0
375 %res = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
376 ret <2 x double> %res
378 declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
381 define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) {
382 ; CHECK-LABEL: test_x86_sse2_movmsk_pd:
384 ; CHECK-NEXT: vmovmskpd %xmm0, %eax
386 %res = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) ; <i32> [#uses=1]
389 declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone
394 define <2 x double> @test_x86_sse2_mul_sd(<2 x double> %a0, <2 x double> %a1) {
395 ; CHECK-LABEL: test_x86_sse2_mul_sd:
397 ; CHECK-NEXT: vmulsd %xmm1, %xmm0, %xmm0
399 %res = call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
400 ret <2 x double> %res
402 declare <2 x double> @llvm.x86.sse2.mul.sd(<2 x double>, <2 x double>) nounwind readnone
405 define <8 x i16> @test_x86_sse2_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) {
406 ; CHECK-LABEL: test_x86_sse2_packssdw_128:
408 ; CHECK-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
410 %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1]
413 declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind readnone
416 define <16 x i8> @test_x86_sse2_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) {
417 ; CHECK-LABEL: test_x86_sse2_packsswb_128:
419 ; CHECK-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
421 %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1]
424 declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind readnone
427 define <16 x i8> @test_x86_sse2_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) {
428 ; CHECK-LABEL: test_x86_sse2_packuswb_128:
430 ; CHECK-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
432 %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1]
435 declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind readnone
438 define <16 x i8> @test_x86_sse2_padds_b(<16 x i8> %a0, <16 x i8> %a1) {
439 ; CHECK-LABEL: test_x86_sse2_padds_b:
441 ; CHECK-NEXT: vpaddsb %xmm1, %xmm0, %xmm0
443 %res = call <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
446 declare <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8>, <16 x i8>) nounwind readnone
449 define <8 x i16> @test_x86_sse2_padds_w(<8 x i16> %a0, <8 x i16> %a1) {
450 ; CHECK-LABEL: test_x86_sse2_padds_w:
452 ; CHECK-NEXT: vpaddsw %xmm1, %xmm0, %xmm0
454 %res = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
457 declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16>, <8 x i16>) nounwind readnone
460 define <16 x i8> @test_x86_sse2_paddus_b(<16 x i8> %a0, <16 x i8> %a1) {
461 ; CHECK-LABEL: test_x86_sse2_paddus_b:
463 ; CHECK-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
465 %res = call <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
468 declare <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8>, <16 x i8>) nounwind readnone
471 define <8 x i16> @test_x86_sse2_paddus_w(<8 x i16> %a0, <8 x i16> %a1) {
472 ; CHECK-LABEL: test_x86_sse2_paddus_w:
474 ; CHECK-NEXT: vpaddusw %xmm1, %xmm0, %xmm0
476 %res = call <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
479 declare <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16>, <8 x i16>) nounwind readnone
482 define <16 x i8> @test_x86_sse2_pavg_b(<16 x i8> %a0, <16 x i8> %a1) {
483 ; CHECK-LABEL: test_x86_sse2_pavg_b:
485 ; CHECK-NEXT: vpavgb %xmm1, %xmm0, %xmm0
487 %res = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
490 declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8>, <16 x i8>) nounwind readnone
493 define <8 x i16> @test_x86_sse2_pavg_w(<8 x i16> %a0, <8 x i16> %a1) {
494 ; CHECK-LABEL: test_x86_sse2_pavg_w:
496 ; CHECK-NEXT: vpavgw %xmm1, %xmm0, %xmm0
498 %res = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
501 declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
504 define <4 x i32> @test_x86_sse2_pmadd_wd(<8 x i16> %a0, <8 x i16> %a1) {
505 ; CHECK-LABEL: test_x86_sse2_pmadd_wd:
507 ; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0
509 %res = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1) ; <<4 x i32>> [#uses=1]
512 declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone
515 define <8 x i16> @test_x86_sse2_pmaxs_w(<8 x i16> %a0, <8 x i16> %a1) {
516 ; CHECK-LABEL: test_x86_sse2_pmaxs_w:
518 ; CHECK-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
520 %res = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
523 declare <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16>, <8 x i16>) nounwind readnone
526 define <16 x i8> @test_x86_sse2_pmaxu_b(<16 x i8> %a0, <16 x i8> %a1) {
527 ; CHECK-LABEL: test_x86_sse2_pmaxu_b:
529 ; CHECK-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
531 %res = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
534 declare <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8>, <16 x i8>) nounwind readnone
537 define <8 x i16> @test_x86_sse2_pmins_w(<8 x i16> %a0, <8 x i16> %a1) {
538 ; CHECK-LABEL: test_x86_sse2_pmins_w:
540 ; CHECK-NEXT: vpminsw %xmm1, %xmm0, %xmm0
542 %res = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
545 declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) nounwind readnone
548 define <16 x i8> @test_x86_sse2_pminu_b(<16 x i8> %a0, <16 x i8> %a1) {
549 ; CHECK-LABEL: test_x86_sse2_pminu_b:
551 ; CHECK-NEXT: vpminub %xmm1, %xmm0, %xmm0
553 %res = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
556 declare <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8>, <16 x i8>) nounwind readnone
559 define i32 @test_x86_sse2_pmovmskb_128(<16 x i8> %a0) {
560 ; CHECK-LABEL: test_x86_sse2_pmovmskb_128:
562 ; CHECK-NEXT: vpmovmskb %xmm0, %eax
564 %res = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0) ; <i32> [#uses=1]
567 declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>) nounwind readnone
570 define <8 x i16> @test_x86_sse2_pmulh_w(<8 x i16> %a0, <8 x i16> %a1) {
571 ; CHECK-LABEL: test_x86_sse2_pmulh_w:
573 ; CHECK-NEXT: vpmulhw %xmm1, %xmm0, %xmm0
575 %res = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
578 declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone
581 define <8 x i16> @test_x86_sse2_pmulhu_w(<8 x i16> %a0, <8 x i16> %a1) {
582 ; CHECK-LABEL: test_x86_sse2_pmulhu_w:
584 ; CHECK-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0
586 %res = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
589 declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone
592 define <2 x i64> @test_x86_sse2_pmulu_dq(<4 x i32> %a0, <4 x i32> %a1) {
593 ; CHECK-LABEL: test_x86_sse2_pmulu_dq:
595 ; CHECK-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
597 %res = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1]
600 declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnone
603 define <2 x i64> @test_x86_sse2_psad_bw(<16 x i8> %a0, <16 x i8> %a1) {
604 ; CHECK-LABEL: test_x86_sse2_psad_bw:
606 ; CHECK-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
608 %res = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1) ; <<2 x i64>> [#uses=1]
611 declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone
614 define <4 x i32> @test_x86_sse2_psll_d(<4 x i32> %a0, <4 x i32> %a1) {
615 ; CHECK-LABEL: test_x86_sse2_psll_d:
617 ; CHECK-NEXT: vpslld %xmm1, %xmm0, %xmm0
619 %res = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
622 declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
625 define <2 x i64> @test_x86_sse2_psll_q(<2 x i64> %a0, <2 x i64> %a1) {
626 ; CHECK-LABEL: test_x86_sse2_psll_q:
628 ; CHECK-NEXT: vpsllq %xmm1, %xmm0, %xmm0
630 %res = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
633 declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) nounwind readnone
636 define <8 x i16> @test_x86_sse2_psll_w(<8 x i16> %a0, <8 x i16> %a1) {
637 ; CHECK-LABEL: test_x86_sse2_psll_w:
639 ; CHECK-NEXT: vpsllw %xmm1, %xmm0, %xmm0
641 %res = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
644 declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
647 define <4 x i32> @test_x86_sse2_pslli_d(<4 x i32> %a0) {
648 ; CHECK-LABEL: test_x86_sse2_pslli_d:
650 ; CHECK-NEXT: vpslld $7, %xmm0, %xmm0
652 %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]
655 declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) nounwind readnone
658 define <2 x i64> @test_x86_sse2_pslli_q(<2 x i64> %a0) {
659 ; CHECK-LABEL: test_x86_sse2_pslli_q:
661 ; CHECK-NEXT: vpsllq $7, %xmm0, %xmm0
663 %res = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
666 declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone
669 define <8 x i16> @test_x86_sse2_pslli_w(<8 x i16> %a0) {
670 ; CHECK-LABEL: test_x86_sse2_pslli_w:
672 ; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0
674 %res = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]
677 declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) nounwind readnone
680 define <4 x i32> @test_x86_sse2_psra_d(<4 x i32> %a0, <4 x i32> %a1) {
681 ; CHECK-LABEL: test_x86_sse2_psra_d:
683 ; CHECK-NEXT: vpsrad %xmm1, %xmm0, %xmm0
685 %res = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
688 declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) nounwind readnone
691 define <8 x i16> @test_x86_sse2_psra_w(<8 x i16> %a0, <8 x i16> %a1) {
692 ; CHECK-LABEL: test_x86_sse2_psra_w:
694 ; CHECK-NEXT: vpsraw %xmm1, %xmm0, %xmm0
696 %res = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
699 declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
702 define <4 x i32> @test_x86_sse2_psrai_d(<4 x i32> %a0) {
703 ; CHECK-LABEL: test_x86_sse2_psrai_d:
705 ; CHECK-NEXT: vpsrad $7, %xmm0, %xmm0
707 %res = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]
710 declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32) nounwind readnone
713 define <8 x i16> @test_x86_sse2_psrai_w(<8 x i16> %a0) {
714 ; CHECK-LABEL: test_x86_sse2_psrai_w:
716 ; CHECK-NEXT: vpsraw $7, %xmm0, %xmm0
718 %res = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]
721 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone
724 define <4 x i32> @test_x86_sse2_psrl_d(<4 x i32> %a0, <4 x i32> %a1) {
725 ; CHECK-LABEL: test_x86_sse2_psrl_d:
727 ; CHECK-NEXT: vpsrld %xmm1, %xmm0, %xmm0
729 %res = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
732 declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone
735 define <2 x i64> @test_x86_sse2_psrl_q(<2 x i64> %a0, <2 x i64> %a1) {
736 ; CHECK-LABEL: test_x86_sse2_psrl_q:
738 ; CHECK-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
740 %res = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
743 declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
746 define <8 x i16> @test_x86_sse2_psrl_w(<8 x i16> %a0, <8 x i16> %a1) {
747 ; CHECK-LABEL: test_x86_sse2_psrl_w:
749 ; CHECK-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
751 %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
754 declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone
757 define <4 x i32> @test_x86_sse2_psrli_d(<4 x i32> %a0) {
758 ; CHECK-LABEL: test_x86_sse2_psrli_d:
760 ; CHECK-NEXT: vpsrld $7, %xmm0, %xmm0
762 %res = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]
765 declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32) nounwind readnone
768 define <2 x i64> @test_x86_sse2_psrli_q(<2 x i64> %a0) {
769 ; CHECK-LABEL: test_x86_sse2_psrli_q:
771 ; CHECK-NEXT: vpsrlq $7, %xmm0, %xmm0
773 %res = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
776 declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32) nounwind readnone
779 define <8 x i16> @test_x86_sse2_psrli_w(<8 x i16> %a0) {
780 ; CHECK-LABEL: test_x86_sse2_psrli_w:
782 ; CHECK-NEXT: vpsrlw $7, %xmm0, %xmm0
784 %res = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]
787 declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) nounwind readnone
790 define <16 x i8> @test_x86_sse2_psubs_b(<16 x i8> %a0, <16 x i8> %a1) {
791 ; CHECK-LABEL: test_x86_sse2_psubs_b:
793 ; CHECK-NEXT: vpsubsb %xmm1, %xmm0, %xmm0
795 %res = call <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
798 declare <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8>, <16 x i8>) nounwind readnone
801 define <8 x i16> @test_x86_sse2_psubs_w(<8 x i16> %a0, <8 x i16> %a1) {
802 ; CHECK-LABEL: test_x86_sse2_psubs_w:
804 ; CHECK-NEXT: vpsubsw %xmm1, %xmm0, %xmm0
806 %res = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
809 declare <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16>, <8 x i16>) nounwind readnone
812 define <16 x i8> @test_x86_sse2_psubus_b(<16 x i8> %a0, <16 x i8> %a1) {
813 ; CHECK-LABEL: test_x86_sse2_psubus_b:
815 ; CHECK-NEXT: vpsubusb %xmm1, %xmm0, %xmm0
817 %res = call <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
820 declare <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8>, <16 x i8>) nounwind readnone
823 define <8 x i16> @test_x86_sse2_psubus_w(<8 x i16> %a0, <8 x i16> %a1) {
824 ; CHECK-LABEL: test_x86_sse2_psubus_w:
826 ; CHECK-NEXT: vpsubusw %xmm1, %xmm0, %xmm0
828 %res = call <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
831 declare <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16>, <8 x i16>) nounwind readnone
834 define <2 x double> @test_x86_sse2_sqrt_pd(<2 x double> %a0) {
835 ; CHECK-LABEL: test_x86_sse2_sqrt_pd:
837 ; CHECK-NEXT: vsqrtpd %xmm0, %xmm0
839 %res = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %a0) ; <<2 x double>> [#uses=1]
840 ret <2 x double> %res
842 declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone
845 define <2 x double> @test_x86_sse2_sqrt_sd(<2 x double> %a0) {
846 ; CHECK-LABEL: test_x86_sse2_sqrt_sd:
848 ; CHECK-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
850 %res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0) ; <<2 x double>> [#uses=1]
851 ret <2 x double> %res
853 declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
856 define void @test_x86_sse2_storel_dq(i8* %a0, <4 x i32> %a1) {
857 ; CHECK-LABEL: test_x86_sse2_storel_dq:
859 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
860 ; CHECK-NEXT: vmovlps %xmm0, (%eax)
862 call void @llvm.x86.sse2.storel.dq(i8* %a0, <4 x i32> %a1)
865 declare void @llvm.x86.sse2.storel.dq(i8*, <4 x i32>) nounwind
868 define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) {
869 ; add operation forces the execution domain.
870 ; CHECK-LABEL: test_x86_sse2_storeu_dq:
872 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
873 ; CHECK-NEXT: vpaddb LCPI77_0, %xmm0, %xmm0
874 ; CHECK-NEXT: vmovdqu %xmm0, (%eax)
876 %a2 = add <16 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
877 call void @llvm.x86.sse2.storeu.dq(i8* %a0, <16 x i8> %a2)
880 declare void @llvm.x86.sse2.storeu.dq(i8*, <16 x i8>) nounwind
883 define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
884 ; fadd operation forces the execution domain.
885 ; CHECK-LABEL: test_x86_sse2_storeu_pd:
887 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
888 ; CHECK-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
889 ; CHECK-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
890 ; CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0
891 ; CHECK-NEXT: vmovupd %xmm0, (%eax)
893 %a2 = fadd <2 x double> %a1, <double 0x0, double 0x4200000000000000>
894 call void @llvm.x86.sse2.storeu.pd(i8* %a0, <2 x double> %a2)
897 declare void @llvm.x86.sse2.storeu.pd(i8*, <2 x double>) nounwind
900 define <2 x double> @test_x86_sse2_sub_sd(<2 x double> %a0, <2 x double> %a1) {
901 ; CHECK-LABEL: test_x86_sse2_sub_sd:
903 ; CHECK-NEXT: vsubsd %xmm1, %xmm0, %xmm0
905 %res = call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
906 ret <2 x double> %res
908 declare <2 x double> @llvm.x86.sse2.sub.sd(<2 x double>, <2 x double>) nounwind readnone
911 define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) {
912 ; CHECK-LABEL: test_x86_sse2_ucomieq_sd:
914 ; CHECK-NEXT: vucomisd %xmm1, %xmm0
915 ; CHECK-NEXT: sete %al
916 ; CHECK-NEXT: movzbl %al, %eax
918 %res = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
921 declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readnone
924 define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) {
925 ; CHECK-LABEL: test_x86_sse2_ucomige_sd:
927 ; CHECK-NEXT: vucomisd %xmm1, %xmm0
928 ; CHECK-NEXT: setae %al
929 ; CHECK-NEXT: movzbl %al, %eax
931 %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
934 declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>) nounwind readnone
937 define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) {
938 ; CHECK-LABEL: test_x86_sse2_ucomigt_sd:
940 ; CHECK-NEXT: vucomisd %xmm1, %xmm0
941 ; CHECK-NEXT: seta %al
942 ; CHECK-NEXT: movzbl %al, %eax
944 %res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
947 declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>) nounwind readnone
950 define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) {
951 ; CHECK-LABEL: test_x86_sse2_ucomile_sd:
953 ; CHECK-NEXT: vucomisd %xmm1, %xmm0
954 ; CHECK-NEXT: setbe %al
955 ; CHECK-NEXT: movzbl %al, %eax
957 %res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
960 declare i32 @llvm.x86.sse2.ucomile.sd(<2 x double>, <2 x double>) nounwind readnone
963 define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) {
964 ; CHECK-LABEL: test_x86_sse2_ucomilt_sd:
966 ; CHECK-NEXT: vucomisd %xmm1, %xmm0
967 ; CHECK-NEXT: sbbl %eax, %eax
968 ; CHECK-NEXT: andl $1, %eax
970 %res = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
973 declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readnone
976 define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) {
977 ; CHECK-LABEL: test_x86_sse2_ucomineq_sd:
979 ; CHECK-NEXT: vucomisd %xmm1, %xmm0
980 ; CHECK-NEXT: setne %al
981 ; CHECK-NEXT: movzbl %al, %eax
983 %res = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
986 declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>) nounwind readnone
989 define <2 x double> @test_x86_sse3_addsub_pd(<2 x double> %a0, <2 x double> %a1) {
990 ; CHECK-LABEL: test_x86_sse3_addsub_pd:
992 ; CHECK-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0
994 %res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
995 ret <2 x double> %res
997 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
1000 define <4 x float> @test_x86_sse3_addsub_ps(<4 x float> %a0, <4 x float> %a1) {
1001 ; CHECK-LABEL: test_x86_sse3_addsub_ps:
1003 ; CHECK-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
1005 %res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1006 ret <4 x float> %res
1008 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
1011 define <2 x double> @test_x86_sse3_hadd_pd(<2 x double> %a0, <2 x double> %a1) {
1012 ; CHECK-LABEL: test_x86_sse3_hadd_pd:
1014 ; CHECK-NEXT: vhaddpd %xmm1, %xmm0, %xmm0
1016 %res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
1017 ret <2 x double> %res
1019 declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone
1022 define <4 x float> @test_x86_sse3_hadd_ps(<4 x float> %a0, <4 x float> %a1) {
1023 ; CHECK-LABEL: test_x86_sse3_hadd_ps:
1025 ; CHECK-NEXT: vhaddps %xmm1, %xmm0, %xmm0
1027 %res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1028 ret <4 x float> %res
1030 declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
1033 define <2 x double> @test_x86_sse3_hsub_pd(<2 x double> %a0, <2 x double> %a1) {
1034 ; CHECK-LABEL: test_x86_sse3_hsub_pd:
1036 ; CHECK-NEXT: vhsubpd %xmm1, %xmm0, %xmm0
1038 %res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
1039 ret <2 x double> %res
1041 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
1044 define <4 x float> @test_x86_sse3_hsub_ps(<4 x float> %a0, <4 x float> %a1) {
1045 ; CHECK-LABEL: test_x86_sse3_hsub_ps:
1047 ; CHECK-NEXT: vhsubps %xmm1, %xmm0, %xmm0
1049 %res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1050 ret <4 x float> %res
1052 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
1055 define <16 x i8> @test_x86_sse3_ldu_dq(i8* %a0) {
1056 ; CHECK-LABEL: test_x86_sse3_ldu_dq:
1058 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
1059 ; CHECK-NEXT: vlddqu (%eax), %xmm0
1061 %res = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %a0) ; <<16 x i8>> [#uses=1]
1064 declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8*) nounwind readonly
1067 define <2 x double> @test_x86_sse41_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
1068 ; CHECK-LABEL: test_x86_sse41_blendvpd:
1070 ; CHECK-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0
1072 %res = call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) ; <<2 x double>> [#uses=1]
1073 ret <2 x double> %res
1075 declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
1078 define <4 x float> @test_x86_sse41_blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
1079 ; CHECK-LABEL: test_x86_sse41_blendvps:
1081 ; CHECK-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
1083 %res = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) ; <<4 x float>> [#uses=1]
1084 ret <4 x float> %res
1086 declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
1089 define <2 x double> @test_x86_sse41_dppd(<2 x double> %a0, <2 x double> %a1) {
1090 ; CHECK-LABEL: test_x86_sse41_dppd:
1092 ; CHECK-NEXT: vdppd $7, %xmm1, %xmm0, %xmm0
1094 %res = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
1095 ret <2 x double> %res
1097 declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i8) nounwind readnone
1100 define <4 x float> @test_x86_sse41_dpps(<4 x float> %a0, <4 x float> %a1) {
1101 ; CHECK-LABEL: test_x86_sse41_dpps:
1103 ; CHECK-NEXT: vdpps $7, %xmm1, %xmm0, %xmm0
1105 %res = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
1106 ret <4 x float> %res
1108 declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i8) nounwind readnone
1111 define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) {
1112 ; CHECK-LABEL: test_x86_sse41_insertps:
1114 ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[3]
1116 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
1117 ret <4 x float> %res
1119 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone
1123 define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
1124 ; CHECK-LABEL: test_x86_sse41_mpsadbw:
1126 ; CHECK-NEXT: vmpsadbw $7, %xmm1, %xmm0, %xmm0
1128 %res = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<8 x i16>> [#uses=1]
1131 declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i8) nounwind readnone
1134 define <8 x i16> @test_x86_sse41_packusdw(<4 x i32> %a0, <4 x i32> %a1) {
1135 ; CHECK-LABEL: test_x86_sse41_packusdw:
1137 ; CHECK-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
1139 %res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1]
1142 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readnone
1145 define <16 x i8> @test_x86_sse41_pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) {
1146 ; CHECK-LABEL: test_x86_sse41_pblendvb:
1148 ; CHECK-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
1150 %res = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) ; <<16 x i8>> [#uses=1]
1153 declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
1156 define <8 x i16> @test_x86_sse41_phminposuw(<8 x i16> %a0) {
1157 ; CHECK-LABEL: test_x86_sse41_phminposuw:
1159 ; CHECK-NEXT: vphminposuw %xmm0, %xmm0
1161 %res = call <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16> %a0) ; <<8 x i16>> [#uses=1]
1164 declare <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16>) nounwind readnone
1167 define <16 x i8> @test_x86_sse41_pmaxsb(<16 x i8> %a0, <16 x i8> %a1) {
1168 ; CHECK-LABEL: test_x86_sse41_pmaxsb:
1170 ; CHECK-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
1172 %res = call <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
1175 declare <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8>, <16 x i8>) nounwind readnone
1178 define <4 x i32> @test_x86_sse41_pmaxsd(<4 x i32> %a0, <4 x i32> %a1) {
1179 ; CHECK-LABEL: test_x86_sse41_pmaxsd:
1181 ; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
1183 %res = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
1186 declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
1189 define <4 x i32> @test_x86_sse41_pmaxud(<4 x i32> %a0, <4 x i32> %a1) {
1190 ; CHECK-LABEL: test_x86_sse41_pmaxud:
1192 ; CHECK-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
1194 %res = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
1197 declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
1200 define <8 x i16> @test_x86_sse41_pmaxuw(<8 x i16> %a0, <8 x i16> %a1) {
1201 ; CHECK-LABEL: test_x86_sse41_pmaxuw:
1203 ; CHECK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0
1205 %res = call <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
1208 declare <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16>, <8 x i16>) nounwind readnone
1211 define <16 x i8> @test_x86_sse41_pminsb(<16 x i8> %a0, <16 x i8> %a1) {
1212 ; CHECK-LABEL: test_x86_sse41_pminsb:
1214 ; CHECK-NEXT: vpminsb %xmm1, %xmm0, %xmm0
1216 %res = call <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
1219 declare <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8>, <16 x i8>) nounwind readnone
1222 define <4 x i32> @test_x86_sse41_pminsd(<4 x i32> %a0, <4 x i32> %a1) {
1223 ; CHECK-LABEL: test_x86_sse41_pminsd:
1225 ; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm0
1227 %res = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
1230 declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
1233 define <4 x i32> @test_x86_sse41_pminud(<4 x i32> %a0, <4 x i32> %a1) {
1234 ; CHECK-LABEL: test_x86_sse41_pminud:
1236 ; CHECK-NEXT: vpminud %xmm1, %xmm0, %xmm0
1238 %res = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
1241 declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
1244 define <8 x i16> @test_x86_sse41_pminuw(<8 x i16> %a0, <8 x i16> %a1) {
1245 ; CHECK-LABEL: test_x86_sse41_pminuw:
1247 ; CHECK-NEXT: vpminuw %xmm1, %xmm0, %xmm0
1249 %res = call <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
1252 declare <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16>, <8 x i16>) nounwind readnone
1255 define <4 x i32> @test_x86_sse41_pmovzxbd(<16 x i8> %a0) {
1256 ; CHECK-LABEL: test_x86_sse41_pmovzxbd:
1258 ; CHECK-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
1260 %res = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1]
1263 declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>) nounwind readnone
1266 define <2 x i64> @test_x86_sse41_pmovzxbq(<16 x i8> %a0) {
1267 ; CHECK-LABEL: test_x86_sse41_pmovzxbq:
1269 ; CHECK-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
1271 %res = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1]
1274 declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
1277 define <8 x i16> @test_x86_sse41_pmovzxbw(<16 x i8> %a0) {
1278 ; CHECK-LABEL: test_x86_sse41_pmovzxbw:
1280 ; CHECK-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
1282 %res = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1]
1285 declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>) nounwind readnone
1288 define <2 x i64> @test_x86_sse41_pmovzxdq(<4 x i32> %a0) {
1289 ; CHECK-LABEL: test_x86_sse41_pmovzxdq:
1291 ; CHECK-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
1293 %res = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1]
1296 declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>) nounwind readnone
1299 define <4 x i32> @test_x86_sse41_pmovzxwd(<8 x i16> %a0) {
1300 ; CHECK-LABEL: test_x86_sse41_pmovzxwd:
1302 ; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
1304 %res = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1]
1307 declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
1310 define <2 x i64> @test_x86_sse41_pmovzxwq(<8 x i16> %a0) {
1311 ; CHECK-LABEL: test_x86_sse41_pmovzxwq:
1313 ; CHECK-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
1315 %res = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1]
1318 declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>) nounwind readnone
1321 define <2 x i64> @test_x86_sse41_pmuldq(<4 x i32> %a0, <4 x i32> %a1) {
1322 ; CHECK-LABEL: test_x86_sse41_pmuldq:
1324 ; CHECK-NEXT: vpmuldq %xmm1, %xmm0, %xmm0
1326 %res = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1]
1329 declare <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32>, <4 x i32>) nounwind readnone
1332 define i32 @test_x86_sse41_ptestc(<2 x i64> %a0, <2 x i64> %a1) {
1333 ; CHECK-LABEL: test_x86_sse41_ptestc:
1335 ; CHECK-NEXT: vptest %xmm1, %xmm0
1336 ; CHECK-NEXT: sbbl %eax, %eax
1337 ; CHECK-NEXT: andl $1, %eax
1339 %res = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
1342 declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
1345 define i32 @test_x86_sse41_ptestnzc(<2 x i64> %a0, <2 x i64> %a1) {
1346 ; CHECK-LABEL: test_x86_sse41_ptestnzc:
1348 ; CHECK-NEXT: vptest %xmm1, %xmm0
1349 ; CHECK-NEXT: seta %al
1350 ; CHECK-NEXT: movzbl %al, %eax
1352 %res = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
1355 declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
1358 define i32 @test_x86_sse41_ptestz(<2 x i64> %a0, <2 x i64> %a1) {
1359 ; CHECK-LABEL: test_x86_sse41_ptestz:
1361 ; CHECK-NEXT: vptest %xmm1, %xmm0
1362 ; CHECK-NEXT: sete %al
1363 ; CHECK-NEXT: movzbl %al, %eax
1365 %res = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
1368 declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
1371 define <2 x double> @test_x86_sse41_round_pd(<2 x double> %a0) {
1372 ; CHECK-LABEL: test_x86_sse41_round_pd:
1374 ; CHECK-NEXT: vroundpd $7, %xmm0, %xmm0
1376 %res = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> %a0, i32 7) ; <<2 x double>> [#uses=1]
1377 ret <2 x double> %res
1379 declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readnone
1382 define <4 x float> @test_x86_sse41_round_ps(<4 x float> %a0) {
1383 ; CHECK-LABEL: test_x86_sse41_round_ps:
1385 ; CHECK-NEXT: vroundps $7, %xmm0, %xmm0
1387 %res = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %a0, i32 7) ; <<4 x float>> [#uses=1]
1388 ret <4 x float> %res
1390 declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
1393 define <2 x double> @test_x86_sse41_round_sd(<2 x double> %a0, <2 x double> %a1) {
1394 ; CHECK-LABEL: test_x86_sse41_round_sd:
1396 ; CHECK-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm0
1398 %res = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1]
1399 ret <2 x double> %res
1401 declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
1404 define <4 x float> @test_x86_sse41_round_ss(<4 x float> %a0, <4 x float> %a1) {
1405 ; CHECK-LABEL: test_x86_sse41_round_ss:
1407 ; CHECK-NEXT: vroundss $7, %xmm1, %xmm0, %xmm0
1409 %res = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
1410 ret <4 x float> %res
1412 declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone
1415 define i32 @test_x86_sse42_pcmpestri128(<16 x i8> %a0, <16 x i8> %a2) {
1416 ; CHECK-LABEL: test_x86_sse42_pcmpestri128:
1418 ; CHECK-NEXT: movl $7, %eax
1419 ; CHECK-NEXT: movl $7, %edx
1420 ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0
1421 ; CHECK-NEXT: movl %ecx, %eax
1423 %res = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
1426 declare i32 @llvm.x86.sse42.pcmpestri128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
1429 define i32 @test_x86_sse42_pcmpestri128_load(<16 x i8>* %a0, <16 x i8>* %a2) {
1430 ; CHECK-LABEL: test_x86_sse42_pcmpestri128_load:
1432 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
1433 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
1434 ; CHECK-NEXT: vmovdqa (%eax), %xmm0
1435 ; CHECK-NEXT: movl $7, %eax
1436 ; CHECK-NEXT: movl $7, %edx
1437 ; CHECK-NEXT: vpcmpestri $7, (%ecx), %xmm0
1438 ; CHECK-NEXT: movl %ecx, %eax
1440 %1 = load <16 x i8>, <16 x i8>* %a0
1441 %2 = load <16 x i8>, <16 x i8>* %a2
1442 %res = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %1, i32 7, <16 x i8> %2, i32 7, i8 7) ; <i32> [#uses=1]
1447 define i32 @test_x86_sse42_pcmpestria128(<16 x i8> %a0, <16 x i8> %a2) {
1448 ; CHECK-LABEL: test_x86_sse42_pcmpestria128:
1450 ; CHECK-NEXT: movl $7, %eax
1451 ; CHECK-NEXT: movl $7, %edx
1452 ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0
1453 ; CHECK-NEXT: seta %al
1454 ; CHECK-NEXT: movzbl %al, %eax
1456 %res = call i32 @llvm.x86.sse42.pcmpestria128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
1459 declare i32 @llvm.x86.sse42.pcmpestria128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
1462 define i32 @test_x86_sse42_pcmpestric128(<16 x i8> %a0, <16 x i8> %a2) {
1463 ; CHECK-LABEL: test_x86_sse42_pcmpestric128:
1465 ; CHECK-NEXT: movl $7, %eax
1466 ; CHECK-NEXT: movl $7, %edx
1467 ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0
1468 ; CHECK-NEXT: sbbl %eax, %eax
1469 ; CHECK-NEXT: andl $1, %eax
1471 %res = call i32 @llvm.x86.sse42.pcmpestric128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
1474 declare i32 @llvm.x86.sse42.pcmpestric128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
1477 define i32 @test_x86_sse42_pcmpestrio128(<16 x i8> %a0, <16 x i8> %a2) {
1478 ; CHECK-LABEL: test_x86_sse42_pcmpestrio128:
1480 ; CHECK-NEXT: movl $7, %eax
1481 ; CHECK-NEXT: movl $7, %edx
1482 ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0
1483 ; CHECK-NEXT: seto %al
1484 ; CHECK-NEXT: movzbl %al, %eax
1486 %res = call i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
1489 declare i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
1492 define i32 @test_x86_sse42_pcmpestris128(<16 x i8> %a0, <16 x i8> %a2) {
1493 ; CHECK-LABEL: test_x86_sse42_pcmpestris128:
1495 ; CHECK-NEXT: movl $7, %eax
1496 ; CHECK-NEXT: movl $7, %edx
1497 ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0
1498 ; CHECK-NEXT: sets %al
1499 ; CHECK-NEXT: movzbl %al, %eax
1501 %res = call i32 @llvm.x86.sse42.pcmpestris128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
1504 declare i32 @llvm.x86.sse42.pcmpestris128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
1507 define i32 @test_x86_sse42_pcmpestriz128(<16 x i8> %a0, <16 x i8> %a2) {
1508 ; CHECK-LABEL: test_x86_sse42_pcmpestriz128:
1510 ; CHECK-NEXT: movl $7, %eax
1511 ; CHECK-NEXT: movl $7, %edx
1512 ; CHECK-NEXT: vpcmpestri $7, %xmm1, %xmm0
1513 ; CHECK-NEXT: sete %al
1514 ; CHECK-NEXT: movzbl %al, %eax
1516 %res = call i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
1519 declare i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
1522 define <16 x i8> @test_x86_sse42_pcmpestrm128(<16 x i8> %a0, <16 x i8> %a2) {
1523 ; CHECK-LABEL: test_x86_sse42_pcmpestrm128:
1525 ; CHECK-NEXT: movl $7, %eax
1526 ; CHECK-NEXT: movl $7, %edx
1527 ; CHECK-NEXT: vpcmpestrm $7, %xmm1, %xmm0
1529 %res = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <<16 x i8>> [#uses=1]
1532 declare <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
1535 define <16 x i8> @test_x86_sse42_pcmpestrm128_load(<16 x i8> %a0, <16 x i8>* %a2) {
1536 ; CHECK-LABEL: test_x86_sse42_pcmpestrm128_load:
1538 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
1539 ; CHECK-NEXT: movl $7, %eax
1540 ; CHECK-NEXT: movl $7, %edx
1541 ; CHECK-NEXT: vpcmpestrm $7, (%ecx), %xmm0
1543 %1 = load <16 x i8>, <16 x i8>* %a2
1544 %res = call <16 x i8> @llvm.x86.sse42.pcmpestrm128(<16 x i8> %a0, i32 7, <16 x i8> %1, i32 7, i8 7) ; <<16 x i8>> [#uses=1]
1549 define i32 @test_x86_sse42_pcmpistri128(<16 x i8> %a0, <16 x i8> %a1) {
1550 ; CHECK-LABEL: test_x86_sse42_pcmpistri128:
1552 ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0
1553 ; CHECK-NEXT: movl %ecx, %eax
1555 %res = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
1558 declare i32 @llvm.x86.sse42.pcmpistri128(<16 x i8>, <16 x i8>, i8) nounwind readnone
1561 define i32 @test_x86_sse42_pcmpistri128_load(<16 x i8>* %a0, <16 x i8>* %a1) {
1562 ; CHECK-LABEL: test_x86_sse42_pcmpistri128_load:
1564 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
1565 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
1566 ; CHECK-NEXT: vmovdqa (%ecx), %xmm0
1567 ; CHECK-NEXT: vpcmpistri $7, (%eax), %xmm0
1568 ; CHECK-NEXT: movl %ecx, %eax
1570 %1 = load <16 x i8>, <16 x i8>* %a0
1571 %2 = load <16 x i8>, <16 x i8>* %a1
1572 %res = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %1, <16 x i8> %2, i8 7) ; <i32> [#uses=1]
1577 define i32 @test_x86_sse42_pcmpistria128(<16 x i8> %a0, <16 x i8> %a1) {
1578 ; CHECK-LABEL: test_x86_sse42_pcmpistria128:
1580 ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0
1581 ; CHECK-NEXT: seta %al
1582 ; CHECK-NEXT: movzbl %al, %eax
1584 %res = call i32 @llvm.x86.sse42.pcmpistria128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
1587 declare i32 @llvm.x86.sse42.pcmpistria128(<16 x i8>, <16 x i8>, i8) nounwind readnone
1590 define i32 @test_x86_sse42_pcmpistric128(<16 x i8> %a0, <16 x i8> %a1) {
1591 ; CHECK-LABEL: test_x86_sse42_pcmpistric128:
1593 ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0
1594 ; CHECK-NEXT: sbbl %eax, %eax
1595 ; CHECK-NEXT: andl $1, %eax
1597 %res = call i32 @llvm.x86.sse42.pcmpistric128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
1600 declare i32 @llvm.x86.sse42.pcmpistric128(<16 x i8>, <16 x i8>, i8) nounwind readnone
1603 define i32 @test_x86_sse42_pcmpistrio128(<16 x i8> %a0, <16 x i8> %a1) {
1604 ; CHECK-LABEL: test_x86_sse42_pcmpistrio128:
1606 ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0
1607 ; CHECK-NEXT: seto %al
1608 ; CHECK-NEXT: movzbl %al, %eax
1610 %res = call i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
1613 declare i32 @llvm.x86.sse42.pcmpistrio128(<16 x i8>, <16 x i8>, i8) nounwind readnone
1616 define i32 @test_x86_sse42_pcmpistris128(<16 x i8> %a0, <16 x i8> %a1) {
1617 ; CHECK-LABEL: test_x86_sse42_pcmpistris128:
1619 ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0
1620 ; CHECK-NEXT: sets %al
1621 ; CHECK-NEXT: movzbl %al, %eax
1623 %res = call i32 @llvm.x86.sse42.pcmpistris128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
1626 declare i32 @llvm.x86.sse42.pcmpistris128(<16 x i8>, <16 x i8>, i8) nounwind readnone
1629 define i32 @test_x86_sse42_pcmpistriz128(<16 x i8> %a0, <16 x i8> %a1) {
1630 ; CHECK-LABEL: test_x86_sse42_pcmpistriz128:
1632 ; CHECK-NEXT: vpcmpistri $7, %xmm1, %xmm0
1633 ; CHECK-NEXT: sete %al
1634 ; CHECK-NEXT: movzbl %al, %eax
1636 %res = call i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <i32> [#uses=1]
1639 declare i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8>, <16 x i8>, i8) nounwind readnone
1642 define <16 x i8> @test_x86_sse42_pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1) {
1643 ; CHECK-LABEL: test_x86_sse42_pcmpistrm128:
1645 ; CHECK-NEXT: vpcmpistrm $7, %xmm1, %xmm0
1647 %res = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<16 x i8>> [#uses=1]
1650 declare <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8>, <16 x i8>, i8) nounwind readnone
1653 define <16 x i8> @test_x86_sse42_pcmpistrm128_load(<16 x i8> %a0, <16 x i8>* %a1) {
1654 ; CHECK-LABEL: test_x86_sse42_pcmpistrm128_load:
1656 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
1657 ; CHECK-NEXT: vpcmpistrm $7, (%eax), %xmm0
1659 %1 = load <16 x i8>, <16 x i8>* %a1
1660 %res = call <16 x i8> @llvm.x86.sse42.pcmpistrm128(<16 x i8> %a0, <16 x i8> %1, i8 7) ; <<16 x i8>> [#uses=1]
1665 define <4 x float> @test_x86_sse_add_ss(<4 x float> %a0, <4 x float> %a1) {
1666 ; CHECK-LABEL: test_x86_sse_add_ss:
1668 ; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0
1670 %res = call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1671 ret <4 x float> %res
1673 declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>) nounwind readnone
1676 define <4 x float> @test_x86_sse_cmp_ps(<4 x float> %a0, <4 x float> %a1) {
1677 ; CHECK-LABEL: test_x86_sse_cmp_ps:
1679 ; CHECK-NEXT: vcmpordps %xmm1, %xmm0, %xmm0
1681 %res = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
1682 ret <4 x float> %res
1684 declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
1687 define <4 x float> @test_x86_sse_cmp_ss(<4 x float> %a0, <4 x float> %a1) {
1688 ; CHECK-LABEL: test_x86_sse_cmp_ss:
1690 ; CHECK-NEXT: vcmpordss %xmm1, %xmm0, %xmm0
1692 %res = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
1693 ret <4 x float> %res
1695 declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) nounwind readnone
1698 define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1) {
1699 ; CHECK-LABEL: test_x86_sse_comieq_ss:
1701 ; CHECK-NEXT: vcomiss %xmm1, %xmm0
1702 ; CHECK-NEXT: sete %al
1703 ; CHECK-NEXT: movzbl %al, %eax
1705 %res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
1708 declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone
1711 define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) {
1712 ; CHECK-LABEL: test_x86_sse_comige_ss:
1714 ; CHECK-NEXT: vcomiss %xmm1, %xmm0
1715 ; CHECK-NEXT: setae %al
1716 ; CHECK-NEXT: movzbl %al, %eax
1718 %res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
1721 declare i32 @llvm.x86.sse.comige.ss(<4 x float>, <4 x float>) nounwind readnone
1724 define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) {
1725 ; CHECK-LABEL: test_x86_sse_comigt_ss:
1727 ; CHECK-NEXT: vcomiss %xmm1, %xmm0
1728 ; CHECK-NEXT: seta %al
1729 ; CHECK-NEXT: movzbl %al, %eax
1731 %res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
1734 declare i32 @llvm.x86.sse.comigt.ss(<4 x float>, <4 x float>) nounwind readnone
1737 define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) {
1738 ; CHECK-LABEL: test_x86_sse_comile_ss:
1740 ; CHECK-NEXT: vcomiss %xmm1, %xmm0
1741 ; CHECK-NEXT: setbe %al
1742 ; CHECK-NEXT: movzbl %al, %eax
1744 %res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
1747 declare i32 @llvm.x86.sse.comile.ss(<4 x float>, <4 x float>) nounwind readnone
1750 define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) {
1751 ; CHECK-LABEL: test_x86_sse_comilt_ss:
1753 ; CHECK-NEXT: vcomiss %xmm1, %xmm0
1754 ; CHECK-NEXT: sbbl %eax, %eax
1755 ; CHECK-NEXT: andl $1, %eax
1757 %res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
1760 declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>) nounwind readnone
1763 define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1) {
1764 ; CHECK-LABEL: test_x86_sse_comineq_ss:
1766 ; CHECK-NEXT: vcomiss %xmm1, %xmm0
1767 ; CHECK-NEXT: setne %al
1768 ; CHECK-NEXT: movzbl %al, %eax
1770 %res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
1773 declare i32 @llvm.x86.sse.comineq.ss(<4 x float>, <4 x float>) nounwind readnone
1776 define <4 x float> @test_x86_sse_cvtsi2ss(<4 x float> %a0) {
1777 ; CHECK-LABEL: test_x86_sse_cvtsi2ss:
1779 ; CHECK-NEXT: movl $7, %eax
1780 ; CHECK-NEXT: vcvtsi2ssl %eax, %xmm0, %xmm0
1782 %res = call <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float> %a0, i32 7) ; <<4 x float>> [#uses=1]
1783 ret <4 x float> %res
1785 declare <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float>, i32) nounwind readnone
1788 define i32 @test_x86_sse_cvtss2si(<4 x float> %a0) {
1789 ; CHECK-LABEL: test_x86_sse_cvtss2si:
1791 ; CHECK-NEXT: vcvtss2si %xmm0, %eax
1793 %res = call i32 @llvm.x86.sse.cvtss2si(<4 x float> %a0) ; <i32> [#uses=1]
1796 declare i32 @llvm.x86.sse.cvtss2si(<4 x float>) nounwind readnone
1799 define i32 @test_x86_sse_cvttss2si(<4 x float> %a0) {
1800 ; CHECK-LABEL: test_x86_sse_cvttss2si:
1802 ; CHECK-NEXT: vcvttss2si %xmm0, %eax
1804 %res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0) ; <i32> [#uses=1]
1807 declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone
1810 define <4 x float> @test_x86_sse_div_ss(<4 x float> %a0, <4 x float> %a1) {
1811 ; CHECK-LABEL: test_x86_sse_div_ss:
1813 ; CHECK-NEXT: vdivss %xmm1, %xmm0, %xmm0
1815 %res = call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1816 ret <4 x float> %res
1818 declare <4 x float> @llvm.x86.sse.div.ss(<4 x float>, <4 x float>) nounwind readnone
1821 define void @test_x86_sse_ldmxcsr(i8* %a0) {
1822 ; CHECK-LABEL: test_x86_sse_ldmxcsr:
1824 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
1825 ; CHECK-NEXT: vldmxcsr (%eax)
1827 call void @llvm.x86.sse.ldmxcsr(i8* %a0)
1830 declare void @llvm.x86.sse.ldmxcsr(i8*) nounwind
1834 define <4 x float> @test_x86_sse_max_ps(<4 x float> %a0, <4 x float> %a1) {
1835 ; CHECK-LABEL: test_x86_sse_max_ps:
1837 ; CHECK-NEXT: vmaxps %xmm1, %xmm0, %xmm0
1839 %res = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1840 ret <4 x float> %res
1842 declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone
1845 define <4 x float> @test_x86_sse_max_ss(<4 x float> %a0, <4 x float> %a1) {
1846 ; CHECK-LABEL: test_x86_sse_max_ss:
1848 ; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0
1850 %res = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1851 ret <4 x float> %res
1853 declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone
1856 define <4 x float> @test_x86_sse_min_ps(<4 x float> %a0, <4 x float> %a1) {
1857 ; CHECK-LABEL: test_x86_sse_min_ps:
1859 ; CHECK-NEXT: vminps %xmm1, %xmm0, %xmm0
1861 %res = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1862 ret <4 x float> %res
1864 declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
1867 define <4 x float> @test_x86_sse_min_ss(<4 x float> %a0, <4 x float> %a1) {
1868 ; CHECK-LABEL: test_x86_sse_min_ss:
1870 ; CHECK-NEXT: vminss %xmm1, %xmm0, %xmm0
1872 %res = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1873 ret <4 x float> %res
1875 declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone
1878 define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) {
1879 ; CHECK-LABEL: test_x86_sse_movmsk_ps:
1881 ; CHECK-NEXT: vmovmskps %xmm0, %eax
1883 %res = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %a0) ; <i32> [#uses=1]
1886 declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
1890 define <4 x float> @test_x86_sse_mul_ss(<4 x float> %a0, <4 x float> %a1) {
1891 ; CHECK-LABEL: test_x86_sse_mul_ss:
1893 ; CHECK-NEXT: vmulss %xmm1, %xmm0, %xmm0
1895 %res = call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1896 ret <4 x float> %res
1898 declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>) nounwind readnone
1901 define <4 x float> @test_x86_sse_rcp_ps(<4 x float> %a0) {
1902 ; CHECK-LABEL: test_x86_sse_rcp_ps:
1904 ; CHECK-NEXT: vrcpps %xmm0, %xmm0
1906 %res = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
1907 ret <4 x float> %res
1909 declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
1912 define <4 x float> @test_x86_sse_rcp_ss(<4 x float> %a0) {
1913 ; CHECK-LABEL: test_x86_sse_rcp_ss:
1915 ; CHECK-NEXT: vrcpss %xmm0, %xmm0, %xmm0
1917 %res = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
1918 ret <4 x float> %res
1920 declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
1923 define <4 x float> @test_x86_sse_rsqrt_ps(<4 x float> %a0) {
1924 ; CHECK-LABEL: test_x86_sse_rsqrt_ps:
1926 ; CHECK-NEXT: vrsqrtps %xmm0, %xmm0
1928 %res = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
1929 ret <4 x float> %res
1931 declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone
1934 define <4 x float> @test_x86_sse_rsqrt_ss(<4 x float> %a0) {
1935 ; CHECK-LABEL: test_x86_sse_rsqrt_ss:
1937 ; CHECK-NEXT: vrsqrtss %xmm0, %xmm0, %xmm0
1939 %res = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
1940 ret <4 x float> %res
1942 declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
1945 define <4 x float> @test_x86_sse_sqrt_ps(<4 x float> %a0) {
1946 ; CHECK-LABEL: test_x86_sse_sqrt_ps:
1948 ; CHECK-NEXT: vsqrtps %xmm0, %xmm0
1950 %res = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
1951 ret <4 x float> %res
1953 declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
1956 define <4 x float> @test_x86_sse_sqrt_ss(<4 x float> %a0) {
1957 ; CHECK-LABEL: test_x86_sse_sqrt_ss:
1959 ; CHECK-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
1961 %res = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
1962 ret <4 x float> %res
1964 declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
1967 define void @test_x86_sse_stmxcsr(i8* %a0) {
1968 ; CHECK-LABEL: test_x86_sse_stmxcsr:
1970 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
1971 ; CHECK-NEXT: vstmxcsr (%eax)
1973 call void @llvm.x86.sse.stmxcsr(i8* %a0)
1976 declare void @llvm.x86.sse.stmxcsr(i8*) nounwind
1979 define void @test_x86_sse_storeu_ps(i8* %a0, <4 x float> %a1) {
1980 ; CHECK-LABEL: test_x86_sse_storeu_ps:
1982 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
1983 ; CHECK-NEXT: vmovups %xmm0, (%eax)
1985 call void @llvm.x86.sse.storeu.ps(i8* %a0, <4 x float> %a1)
1988 declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
1991 define <4 x float> @test_x86_sse_sub_ss(<4 x float> %a0, <4 x float> %a1) {
1992 ; CHECK-LABEL: test_x86_sse_sub_ss:
1994 ; CHECK-NEXT: vsubss %xmm1, %xmm0, %xmm0
1996 %res = call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
1997 ret <4 x float> %res
1999 declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) nounwind readnone
2002 define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1) {
2003 ; CHECK-LABEL: test_x86_sse_ucomieq_ss:
2005 ; CHECK-NEXT: vucomiss %xmm1, %xmm0
2006 ; CHECK-NEXT: sete %al
2007 ; CHECK-NEXT: movzbl %al, %eax
2009 %res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
2012 declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone
2015 define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) {
2016 ; CHECK-LABEL: test_x86_sse_ucomige_ss:
2018 ; CHECK-NEXT: vucomiss %xmm1, %xmm0
2019 ; CHECK-NEXT: setae %al
2020 ; CHECK-NEXT: movzbl %al, %eax
2022 %res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
2025 declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
2028 define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) {
2029 ; CHECK-LABEL: test_x86_sse_ucomigt_ss:
2031 ; CHECK-NEXT: vucomiss %xmm1, %xmm0
2032 ; CHECK-NEXT: seta %al
2033 ; CHECK-NEXT: movzbl %al, %eax
2035 %res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
2038 declare i32 @llvm.x86.sse.ucomigt.ss(<4 x float>, <4 x float>) nounwind readnone
2041 define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) {
2042 ; CHECK-LABEL: test_x86_sse_ucomile_ss:
2044 ; CHECK-NEXT: vucomiss %xmm1, %xmm0
2045 ; CHECK-NEXT: setbe %al
2046 ; CHECK-NEXT: movzbl %al, %eax
2048 %res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
2051 declare i32 @llvm.x86.sse.ucomile.ss(<4 x float>, <4 x float>) nounwind readnone
2054 define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) {
2055 ; CHECK-LABEL: test_x86_sse_ucomilt_ss:
2057 ; CHECK-NEXT: vucomiss %xmm1, %xmm0
2058 ; CHECK-NEXT: sbbl %eax, %eax
2059 ; CHECK-NEXT: andl $1, %eax
2061 %res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
2064 declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>) nounwind readnone
2067 define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) {
2068 ; CHECK-LABEL: test_x86_sse_ucomineq_ss:
2070 ; CHECK-NEXT: vucomiss %xmm1, %xmm0
2071 ; CHECK-NEXT: setne %al
2072 ; CHECK-NEXT: movzbl %al, %eax
2074 %res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
2077 declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnone
2080 define <16 x i8> @test_x86_ssse3_pabs_b_128(<16 x i8> %a0) {
2081 ; CHECK-LABEL: test_x86_ssse3_pabs_b_128:
2083 ; CHECK-NEXT: vpabsb %xmm0, %xmm0
2085 %res = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0) ; <<16 x i8>> [#uses=1]
2088 declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
2091 define <4 x i32> @test_x86_ssse3_pabs_d_128(<4 x i32> %a0) {
2092 ; CHECK-LABEL: test_x86_ssse3_pabs_d_128:
2094 ; CHECK-NEXT: vpabsd %xmm0, %xmm0
2096 %res = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0) ; <<4 x i32>> [#uses=1]
2099 declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
2102 define <8 x i16> @test_x86_ssse3_pabs_w_128(<8 x i16> %a0) {
2103 ; CHECK-LABEL: test_x86_ssse3_pabs_w_128:
2105 ; CHECK-NEXT: vpabsw %xmm0, %xmm0
2107 %res = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0) ; <<8 x i16>> [#uses=1]
2110 declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
2113 define <4 x i32> @test_x86_ssse3_phadd_d_128(<4 x i32> %a0, <4 x i32> %a1) {
2114 ; CHECK-LABEL: test_x86_ssse3_phadd_d_128:
2116 ; CHECK-NEXT: vphaddd %xmm1, %xmm0, %xmm0
2118 %res = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
2121 declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
2124 define <8 x i16> @test_x86_ssse3_phadd_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
2125 ; CHECK-LABEL: test_x86_ssse3_phadd_sw_128:
2127 ; CHECK-NEXT: vphaddsw %xmm1, %xmm0, %xmm0
2129 %res = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
2132 declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
2135 define <8 x i16> @test_x86_ssse3_phadd_w_128(<8 x i16> %a0, <8 x i16> %a1) {
2136 ; CHECK-LABEL: test_x86_ssse3_phadd_w_128:
2138 ; CHECK-NEXT: vphaddw %xmm1, %xmm0, %xmm0
2140 %res = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
2143 declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind readnone
2146 define <4 x i32> @test_x86_ssse3_phsub_d_128(<4 x i32> %a0, <4 x i32> %a1) {
2147 ; CHECK-LABEL: test_x86_ssse3_phsub_d_128:
2149 ; CHECK-NEXT: vphsubd %xmm1, %xmm0, %xmm0
2151 %res = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
2154 declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind readnone
2157 define <8 x i16> @test_x86_ssse3_phsub_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
2158 ; CHECK-LABEL: test_x86_ssse3_phsub_sw_128:
2160 ; CHECK-NEXT: vphsubsw %xmm1, %xmm0, %xmm0
2162 %res = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
2165 declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
2168 define <8 x i16> @test_x86_ssse3_phsub_w_128(<8 x i16> %a0, <8 x i16> %a1) {
2169 ; CHECK-LABEL: test_x86_ssse3_phsub_w_128:
2171 ; CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0
2173 %res = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
2176 declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind readnone
2179 define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128(<16 x i8> %a0, <16 x i8> %a1) {
2180 ; CHECK-LABEL: test_x86_ssse3_pmadd_ub_sw_128:
2182 ; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0
2184 %res = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8> %a0, <16 x i8> %a1) ; <<8 x i16>> [#uses=1]
2187 declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8>, <16 x i8>) nounwind readnone
2190 define <8 x i16> @test_x86_ssse3_pmul_hr_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
2191 ; CHECK-LABEL: test_x86_ssse3_pmul_hr_sw_128:
2193 ; CHECK-NEXT: vpmulhrsw %xmm1, %xmm0, %xmm0
2195 %res = call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
2198 declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
2201 define <16 x i8> @test_x86_ssse3_pshuf_b_128(<16 x i8> %a0, <16 x i8> %a1) {
2202 ; CHECK-LABEL: test_x86_ssse3_pshuf_b_128:
2204 ; CHECK-NEXT: vpshufb %xmm1, %xmm0, %xmm0
2206 %res = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
2209 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
2212 define <16 x i8> @test_x86_ssse3_psign_b_128(<16 x i8> %a0, <16 x i8> %a1) {
2213 ; CHECK-LABEL: test_x86_ssse3_psign_b_128:
2215 ; CHECK-NEXT: vpsignb %xmm1, %xmm0, %xmm0
2217 %res = call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
2220 declare <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8>, <16 x i8>) nounwind readnone
2223 define <4 x i32> @test_x86_ssse3_psign_d_128(<4 x i32> %a0, <4 x i32> %a1) {
2224 ; CHECK-LABEL: test_x86_ssse3_psign_d_128:
2226 ; CHECK-NEXT: vpsignd %xmm1, %xmm0, %xmm0
2228 %res = call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
2231 declare <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32>, <4 x i32>) nounwind readnone
2234 define <8 x i16> @test_x86_ssse3_psign_w_128(<8 x i16> %a0, <8 x i16> %a1) {
2235 ; CHECK-LABEL: test_x86_ssse3_psign_w_128:
2237 ; CHECK-NEXT: vpsignw %xmm1, %xmm0, %xmm0
2239 %res = call <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
2242 declare <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16>, <8 x i16>) nounwind readnone
2245 define <4 x double> @test_x86_avx_addsub_pd_256(<4 x double> %a0, <4 x double> %a1) {
2246 ; CHECK-LABEL: test_x86_avx_addsub_pd_256:
2248 ; CHECK-NEXT: vaddsubpd %ymm1, %ymm0, %ymm0
2250 %res = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
2251 ret <4 x double> %res
2253 declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
2256 define <8 x float> @test_x86_avx_addsub_ps_256(<8 x float> %a0, <8 x float> %a1) {
2257 ; CHECK-LABEL: test_x86_avx_addsub_ps_256:
2259 ; CHECK-NEXT: vaddsubps %ymm1, %ymm0, %ymm0
2261 %res = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
2262 ret <8 x float> %res
2264 declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
2267 define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) {
2268 ; CHECK-LABEL: test_x86_avx_blendv_pd_256:
2270 ; CHECK-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0
2272 %res = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) ; <<4 x double>> [#uses=1]
2273 ret <4 x double> %res
2275 declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
2278 define <8 x float> @test_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
2279 ; CHECK-LABEL: test_x86_avx_blendv_ps_256:
2281 ; CHECK-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0
2283 %res = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) ; <<8 x float>> [#uses=1]
2284 ret <8 x float> %res
2286 declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
2289 define <4 x double> @test_x86_avx_cmp_pd_256(<4 x double> %a0, <4 x double> %a1) {
2290 ; CHECK-LABEL: test_x86_avx_cmp_pd_256:
2292 ; CHECK-NEXT: vcmpordpd %ymm1, %ymm0, %ymm0
2294 %res = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1]
2295 ret <4 x double> %res
2297 declare <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
2300 define <8 x float> @test_x86_avx_cmp_ps_256(<8 x float> %a0, <8 x float> %a1) {
2301 ; CHECK-LABEL: test_x86_avx_cmp_ps_256:
2303 ; CHECK-NEXT: vcmpordps %ymm1, %ymm0, %ymm0
2305 %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
2306 ret <8 x float> %res
2309 define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x float> %a1) {
2310 ; CHECK-LABEL: test_x86_avx_cmp_ps_256_pseudo_op:
2312 ; CHECK-NEXT: vcmpeqps %ymm1, %ymm0, %ymm1
2313 ; CHECK-NEXT: vcmpltps %ymm1, %ymm0, %ymm1
2314 ; CHECK-NEXT: vcmpleps %ymm1, %ymm0, %ymm1
2315 ; CHECK-NEXT: vcmpunordps %ymm1, %ymm0, %ymm1
2316 ; CHECK-NEXT: vcmpneqps %ymm1, %ymm0, %ymm1
2317 ; CHECK-NEXT: vcmpnltps %ymm1, %ymm0, %ymm1
2318 ; CHECK-NEXT: vcmpnleps %ymm1, %ymm0, %ymm1
2319 ; CHECK-NEXT: vcmpordps %ymm1, %ymm0, %ymm1
2320 ; CHECK-NEXT: vcmpeq_uqps %ymm1, %ymm0, %ymm1
2321 ; CHECK-NEXT: vcmpngeps %ymm1, %ymm0, %ymm1
2322 ; CHECK-NEXT: vcmpngtps %ymm1, %ymm0, %ymm1
2323 ; CHECK-NEXT: vcmpfalseps %ymm1, %ymm0, %ymm1
2324 ; CHECK-NEXT: vcmpneq_oqps %ymm1, %ymm0, %ymm1
2325 ; CHECK-NEXT: vcmpgeps %ymm1, %ymm0, %ymm1
2326 ; CHECK-NEXT: vcmpgtps %ymm1, %ymm0, %ymm1
2327 ; CHECK-NEXT: vcmptrueps %ymm1, %ymm0, %ymm1
2328 ; CHECK-NEXT: vcmpeq_osps %ymm1, %ymm0, %ymm1
2329 ; CHECK-NEXT: vcmplt_oqps %ymm1, %ymm0, %ymm1
2330 ; CHECK-NEXT: vcmple_oqps %ymm1, %ymm0, %ymm1
2331 ; CHECK-NEXT: vcmpunord_sps %ymm1, %ymm0, %ymm1
2332 ; CHECK-NEXT: vcmpneq_usps %ymm1, %ymm0, %ymm1
2333 ; CHECK-NEXT: vcmpnlt_uqps %ymm1, %ymm0, %ymm1
2334 ; CHECK-NEXT: vcmpnle_uqps %ymm1, %ymm0, %ymm1
2335 ; CHECK-NEXT: vcmpord_sps %ymm1, %ymm0, %ymm1
2336 ; CHECK-NEXT: vcmpeq_usps %ymm1, %ymm0, %ymm1
2337 ; CHECK-NEXT: vcmpnge_uqps %ymm1, %ymm0, %ymm1
2338 ; CHECK-NEXT: vcmpngt_uqps %ymm1, %ymm0, %ymm1
2339 ; CHECK-NEXT: vcmpfalse_osps %ymm1, %ymm0, %ymm1
2340 ; CHECK-NEXT: vcmpneq_osps %ymm1, %ymm0, %ymm1
2341 ; CHECK-NEXT: vcmpge_oqps %ymm1, %ymm0, %ymm1
2342 ; CHECK-NEXT: vcmpgt_oqps %ymm1, %ymm0, %ymm1
2343 ; CHECK-NEXT: vcmptrue_usps %ymm1, %ymm0, %ymm0
2345 %a2 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 0) ; <<8 x float>> [#uses=1]
2346 %a3 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a2, i8 1) ; <<8 x float>> [#uses=1]
2347 %a4 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a3, i8 2) ; <<8 x float>> [#uses=1]
2348 %a5 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a4, i8 3) ; <<8 x float>> [#uses=1]
2349 %a6 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a5, i8 4) ; <<8 x float>> [#uses=1]
2350 %a7 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a6, i8 5) ; <<8 x float>> [#uses=1]
2351 %a8 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a7, i8 6) ; <<8 x float>> [#uses=1]
2352 %a9 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a8, i8 7) ; <<8 x float>> [#uses=1]
2353 %a10 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a9, i8 8) ; <<8 x float>> [#uses=1]
2354 %a11 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a10, i8 9) ; <<8 x float>> [#uses=1]
2355 %a12 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a11, i8 10) ; <<8 x float>> [#uses=1]
2356 %a13 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a12, i8 11) ; <<8 x float>> [#uses=1]
2357 %a14 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a13, i8 12) ; <<8 x float>> [#uses=1]
2358 %a15 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a14, i8 13) ; <<8 x float>> [#uses=1]
2359 %a16 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a15, i8 14) ; <<8 x float>> [#uses=1]
2360 %a17 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a16, i8 15) ; <<8 x float>> [#uses=1]
2361 %a18 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a17, i8 16) ; <<8 x float>> [#uses=1]
2362 %a19 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a18, i8 17) ; <<8 x float>> [#uses=1]
2363 %a20 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a19, i8 18) ; <<8 x float>> [#uses=1]
2364 %a21 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a20, i8 19) ; <<8 x float>> [#uses=1]
2365 %a22 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a21, i8 20) ; <<8 x float>> [#uses=1]
2366 %a23 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a22, i8 21) ; <<8 x float>> [#uses=1]
2367 %a24 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a23, i8 22) ; <<8 x float>> [#uses=1]
2368 %a25 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a24, i8 23) ; <<8 x float>> [#uses=1]
2369 %a26 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a25, i8 24) ; <<8 x float>> [#uses=1]
2370 %a27 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a26, i8 25) ; <<8 x float>> [#uses=1]
2371 %a28 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a27, i8 26) ; <<8 x float>> [#uses=1]
2372 %a29 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a28, i8 27) ; <<8 x float>> [#uses=1]
2373 %a30 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a29, i8 28) ; <<8 x float>> [#uses=1]
2374 %a31 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a30, i8 29) ; <<8 x float>> [#uses=1]
2375 %a32 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a31, i8 30) ; <<8 x float>> [#uses=1]
2376 %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a32, i8 31) ; <<8 x float>> [#uses=1]
2377 ret <8 x float> %res
2379 declare <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
2382 define <4 x float> @test_x86_avx_cvt_pd2_ps_256(<4 x double> %a0) {
2383 ; CHECK-LABEL: test_x86_avx_cvt_pd2_ps_256:
2385 ; CHECK-NEXT: vcvtpd2psy %ymm0, %xmm0
2386 ; CHECK-NEXT: vzeroupper
2388 %res = call <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double> %a0) ; <<4 x float>> [#uses=1]
2389 ret <4 x float> %res
2391 declare <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double>) nounwind readnone
2394 define <4 x i32> @test_x86_avx_cvt_pd2dq_256(<4 x double> %a0) {
2395 ; CHECK-LABEL: test_x86_avx_cvt_pd2dq_256:
2397 ; CHECK-NEXT: vcvtpd2dqy %ymm0, %xmm0
2398 ; CHECK-NEXT: vzeroupper
2400 %res = call <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]
2403 declare <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double>) nounwind readnone
2406 define <4 x double> @test_x86_avx_cvt_ps2_pd_256(<4 x float> %a0) {
2407 ; CHECK-LABEL: test_x86_avx_cvt_ps2_pd_256:
2409 ; CHECK-NEXT: vcvtps2pd %xmm0, %ymm0
2411 %res = call <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float> %a0) ; <<4 x double>> [#uses=1]
2412 ret <4 x double> %res
2414 declare <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float>) nounwind readnone
2417 define <8 x i32> @test_x86_avx_cvt_ps2dq_256(<8 x float> %a0) {
2418 ; CHECK-LABEL: test_x86_avx_cvt_ps2dq_256:
2420 ; CHECK-NEXT: vcvtps2dq %ymm0, %ymm0
2422 %res = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]
2425 declare <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float>) nounwind readnone
2428 define <4 x double> @test_x86_avx_cvtdq2_pd_256(<4 x i32> %a0) {
2429 ; CHECK-LABEL: test_x86_avx_cvtdq2_pd_256:
2431 ; CHECK-NEXT: vcvtdq2pd %xmm0, %ymm0
2433 %res = call <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32> %a0) ; <<4 x double>> [#uses=1]
2434 ret <4 x double> %res
2436 declare <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32>) nounwind readnone
2439 define <8 x float> @test_x86_avx_cvtdq2_ps_256(<8 x i32> %a0) {
2440 ; CHECK-LABEL: test_x86_avx_cvtdq2_ps_256:
2442 ; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm0
2444 %res = call <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32> %a0) ; <<8 x float>> [#uses=1]
2445 ret <8 x float> %res
2447 declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) nounwind readnone
2450 define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) {
2451 ; CHECK-LABEL: test_x86_avx_cvtt_pd2dq_256:
2453 ; CHECK-NEXT: vcvttpd2dqy %ymm0, %xmm0
2454 ; CHECK-NEXT: vzeroupper
2456 %res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]
2459 declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone
2462 define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) {
2463 ; CHECK-LABEL: test_x86_avx_cvtt_ps2dq_256:
2465 ; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0
2467 %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]
2470 declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone
2473 define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) {
2474 ; CHECK-LABEL: test_x86_avx_dp_ps_256:
2476 ; CHECK-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0
2478 %res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
2479 ret <8 x float> %res
2481 declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
2484 define <4 x double> @test_x86_avx_hadd_pd_256(<4 x double> %a0, <4 x double> %a1) {
2485 ; CHECK-LABEL: test_x86_avx_hadd_pd_256:
2487 ; CHECK-NEXT: vhaddpd %ymm1, %ymm0, %ymm0
2489 %res = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
2490 ret <4 x double> %res
2492 declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>) nounwind readnone
2495 define <8 x float> @test_x86_avx_hadd_ps_256(<8 x float> %a0, <8 x float> %a1) {
2496 ; CHECK-LABEL: test_x86_avx_hadd_ps_256:
2498 ; CHECK-NEXT: vhaddps %ymm1, %ymm0, %ymm0
2500 %res = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
2501 ret <8 x float> %res
2503 declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) nounwind readnone
2506 define <4 x double> @test_x86_avx_hsub_pd_256(<4 x double> %a0, <4 x double> %a1) {
2507 ; CHECK-LABEL: test_x86_avx_hsub_pd_256:
2509 ; CHECK-NEXT: vhsubpd %ymm1, %ymm0, %ymm0
2511 %res = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
2512 ret <4 x double> %res
2514 declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
2517 define <8 x float> @test_x86_avx_hsub_ps_256(<8 x float> %a0, <8 x float> %a1) {
2518 ; CHECK-LABEL: test_x86_avx_hsub_ps_256:
2520 ; CHECK-NEXT: vhsubps %ymm1, %ymm0, %ymm0
2522 %res = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
2523 ret <8 x float> %res
2525 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
2528 define <32 x i8> @test_x86_avx_ldu_dq_256(i8* %a0) {
2529 ; CHECK-LABEL: test_x86_avx_ldu_dq_256:
2531 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2532 ; CHECK-NEXT: vlddqu (%eax), %ymm0
2534 %res = call <32 x i8> @llvm.x86.avx.ldu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1]
2537 declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly
2540 define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x i64> %mask) {
2541 ; CHECK-LABEL: test_x86_avx_maskload_pd:
2543 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2544 ; CHECK-NEXT: vmaskmovpd (%eax), %xmm0, %xmm0
2546 %res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x i64> %mask) ; <<2 x double>> [#uses=1]
2547 ret <2 x double> %res
2549 declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x i64>) nounwind readonly
2552 define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x i64> %mask) {
2553 ; CHECK-LABEL: test_x86_avx_maskload_pd_256:
2555 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2556 ; CHECK-NEXT: vmaskmovpd (%eax), %ymm0, %ymm0
2558 %res = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %a0, <4 x i64> %mask) ; <<4 x double>> [#uses=1]
2559 ret <4 x double> %res
2561 declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x i64>) nounwind readonly
2564 define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x i32> %mask) {
2565 ; CHECK-LABEL: test_x86_avx_maskload_ps:
2567 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2568 ; CHECK-NEXT: vmaskmovps (%eax), %xmm0, %xmm0
2570 %res = call <4 x float> @llvm.x86.avx.maskload.ps(i8* %a0, <4 x i32> %mask) ; <<4 x float>> [#uses=1]
2571 ret <4 x float> %res
2573 declare <4 x float> @llvm.x86.avx.maskload.ps(i8*, <4 x i32>) nounwind readonly
2576 define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x i32> %mask) {
2577 ; CHECK-LABEL: test_x86_avx_maskload_ps_256:
2579 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2580 ; CHECK-NEXT: vmaskmovps (%eax), %ymm0, %ymm0
2582 %res = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %a0, <8 x i32> %mask) ; <<8 x float>> [#uses=1]
2583 ret <8 x float> %res
2585 declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x i32>) nounwind readonly
2588 define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x i64> %mask, <2 x double> %a2) {
2589 ; CHECK-LABEL: test_x86_avx_maskstore_pd:
2591 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2592 ; CHECK-NEXT: vmaskmovpd %xmm1, %xmm0, (%eax)
2594 call void @llvm.x86.avx.maskstore.pd(i8* %a0, <2 x i64> %mask, <2 x double> %a2)
2597 declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x i64>, <2 x double>) nounwind
2600 define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x i64> %mask, <4 x double> %a2) {
2601 ; CHECK-LABEL: test_x86_avx_maskstore_pd_256:
2603 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2604 ; CHECK-NEXT: vmaskmovpd %ymm1, %ymm0, (%eax)
2605 ; CHECK-NEXT: vzeroupper
2607 call void @llvm.x86.avx.maskstore.pd.256(i8* %a0, <4 x i64> %mask, <4 x double> %a2)
2610 declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x i64>, <4 x double>) nounwind
2613 define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x i32> %mask, <4 x float> %a2) {
2614 ; CHECK-LABEL: test_x86_avx_maskstore_ps:
2616 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2617 ; CHECK-NEXT: vmaskmovps %xmm1, %xmm0, (%eax)
2619 call void @llvm.x86.avx.maskstore.ps(i8* %a0, <4 x i32> %mask, <4 x float> %a2)
2622 declare void @llvm.x86.avx.maskstore.ps(i8*, <4 x i32>, <4 x float>) nounwind
2625 define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x i32> %mask, <8 x float> %a2) {
2626 ; CHECK-LABEL: test_x86_avx_maskstore_ps_256:
2628 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2629 ; CHECK-NEXT: vmaskmovps %ymm1, %ymm0, (%eax)
2630 ; CHECK-NEXT: vzeroupper
2632 call void @llvm.x86.avx.maskstore.ps.256(i8* %a0, <8 x i32> %mask, <8 x float> %a2)
2635 declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>) nounwind
2638 define <4 x double> @test_x86_avx_max_pd_256(<4 x double> %a0, <4 x double> %a1) {
2639 ; CHECK-LABEL: test_x86_avx_max_pd_256:
2641 ; CHECK-NEXT: vmaxpd %ymm1, %ymm0, %ymm0
2643 %res = call <4 x double> @llvm.x86.avx.max.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
2644 ret <4 x double> %res
2646 declare <4 x double> @llvm.x86.avx.max.pd.256(<4 x double>, <4 x double>) nounwind readnone
2649 define <8 x float> @test_x86_avx_max_ps_256(<8 x float> %a0, <8 x float> %a1) {
2650 ; CHECK-LABEL: test_x86_avx_max_ps_256:
2652 ; CHECK-NEXT: vmaxps %ymm1, %ymm0, %ymm0
2654 %res = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
2655 ret <8 x float> %res
2657 declare <8 x float> @llvm.x86.avx.max.ps.256(<8 x float>, <8 x float>) nounwind readnone
2660 define <4 x double> @test_x86_avx_min_pd_256(<4 x double> %a0, <4 x double> %a1) {
2661 ; CHECK-LABEL: test_x86_avx_min_pd_256:
2663 ; CHECK-NEXT: vminpd %ymm1, %ymm0, %ymm0
2665 %res = call <4 x double> @llvm.x86.avx.min.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
2666 ret <4 x double> %res
2668 declare <4 x double> @llvm.x86.avx.min.pd.256(<4 x double>, <4 x double>) nounwind readnone
2671 define <8 x float> @test_x86_avx_min_ps_256(<8 x float> %a0, <8 x float> %a1) {
2672 ; CHECK-LABEL: test_x86_avx_min_ps_256:
2674 ; CHECK-NEXT: vminps %ymm1, %ymm0, %ymm0
2676 %res = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
2677 ret <8 x float> %res
2679 declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>) nounwind readnone
2682 define i32 @test_x86_avx_movmsk_pd_256(<4 x double> %a0) {
2683 ; CHECK-LABEL: test_x86_avx_movmsk_pd_256:
2685 ; CHECK-NEXT: vmovmskpd %ymm0, %eax
2686 ; CHECK-NEXT: vzeroupper
2688 %res = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %a0) ; <i32> [#uses=1]
2691 declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>) nounwind readnone
2694 define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) {
2695 ; CHECK-LABEL: test_x86_avx_movmsk_ps_256:
2697 ; CHECK-NEXT: vmovmskps %ymm0, %eax
2698 ; CHECK-NEXT: vzeroupper
2700 %res = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %a0) ; <i32> [#uses=1]
2703 declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone
2711 define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) {
2712 ; CHECK-LABEL: test_x86_avx_ptestc_256:
2714 ; CHECK-NEXT: vptest %ymm1, %ymm0
2715 ; CHECK-NEXT: sbbl %eax, %eax
2716 ; CHECK-NEXT: andl $1, %eax
2717 ; CHECK-NEXT: vzeroupper
2719 %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
2722 declare i32 @llvm.x86.avx.ptestc.256(<4 x i64>, <4 x i64>) nounwind readnone
2725 define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) {
2726 ; CHECK-LABEL: test_x86_avx_ptestnzc_256:
2728 ; CHECK-NEXT: vptest %ymm1, %ymm0
2729 ; CHECK-NEXT: seta %al
2730 ; CHECK-NEXT: movzbl %al, %eax
2731 ; CHECK-NEXT: vzeroupper
2733 %res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
2736 declare i32 @llvm.x86.avx.ptestnzc.256(<4 x i64>, <4 x i64>) nounwind readnone
2739 define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) {
2740 ; CHECK-LABEL: test_x86_avx_ptestz_256:
2742 ; CHECK-NEXT: vptest %ymm1, %ymm0
2743 ; CHECK-NEXT: sete %al
2744 ; CHECK-NEXT: movzbl %al, %eax
2745 ; CHECK-NEXT: vzeroupper
2747 %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
2750 declare i32 @llvm.x86.avx.ptestz.256(<4 x i64>, <4 x i64>) nounwind readnone
2753 define <8 x float> @test_x86_avx_rcp_ps_256(<8 x float> %a0) {
2754 ; CHECK-LABEL: test_x86_avx_rcp_ps_256:
2756 ; CHECK-NEXT: vrcpps %ymm0, %ymm0
2758 %res = call <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
2759 ret <8 x float> %res
2761 declare <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float>) nounwind readnone
2764 define <4 x double> @test_x86_avx_round_pd_256(<4 x double> %a0) {
2765 ; CHECK-LABEL: test_x86_avx_round_pd_256:
2767 ; CHECK-NEXT: vroundpd $7, %ymm0, %ymm0
2769 %res = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> %a0, i32 7) ; <<4 x double>> [#uses=1]
2770 ret <4 x double> %res
2772 declare <4 x double> @llvm.x86.avx.round.pd.256(<4 x double>, i32) nounwind readnone
2775 define <8 x float> @test_x86_avx_round_ps_256(<8 x float> %a0) {
2776 ; CHECK-LABEL: test_x86_avx_round_ps_256:
2778 ; CHECK-NEXT: vroundps $7, %ymm0, %ymm0
2780 %res = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7) ; <<8 x float>> [#uses=1]
2781 ret <8 x float> %res
2783 declare <8 x float> @llvm.x86.avx.round.ps.256(<8 x float>, i32) nounwind readnone
2786 define <8 x float> @test_x86_avx_rsqrt_ps_256(<8 x float> %a0) {
2787 ; CHECK-LABEL: test_x86_avx_rsqrt_ps_256:
2789 ; CHECK-NEXT: vrsqrtps %ymm0, %ymm0
2791 %res = call <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
2792 ret <8 x float> %res
2794 declare <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float>) nounwind readnone
2797 define <4 x double> @test_x86_avx_sqrt_pd_256(<4 x double> %a0) {
2798 ; CHECK-LABEL: test_x86_avx_sqrt_pd_256:
2800 ; CHECK-NEXT: vsqrtpd %ymm0, %ymm0
2802 %res = call <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double> %a0) ; <<4 x double>> [#uses=1]
2803 ret <4 x double> %res
2805 declare <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double>) nounwind readnone
2808 define <8 x float> @test_x86_avx_sqrt_ps_256(<8 x float> %a0) {
2809 ; CHECK-LABEL: test_x86_avx_sqrt_ps_256:
2811 ; CHECK-NEXT: vsqrtps %ymm0, %ymm0
2813 %res = call <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
2814 ret <8 x float> %res
2816 declare <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float>) nounwind readnone
2819 define void @test_x86_avx_storeu_dq_256(i8* %a0, <32 x i8> %a1) {
2820 ; FIXME: unfortunately the execution domain fix pass changes this to vmovups and its hard to force with no 256-bit integer instructions
2821 ; add operation forces the execution domain.
2822 ; CHECK-LABEL: test_x86_avx_storeu_dq_256:
2824 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2825 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
2826 ; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
2827 ; CHECK-NEXT: vpaddb %xmm2, %xmm1, %xmm1
2828 ; CHECK-NEXT: vpaddb %xmm2, %xmm0, %xmm0
2829 ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
2830 ; CHECK-NEXT: vmovups %ymm0, (%eax)
2831 ; CHECK-NEXT: vzeroupper
2833 %a2 = add <32 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
2834 call void @llvm.x86.avx.storeu.dq.256(i8* %a0, <32 x i8> %a2)
2837 declare void @llvm.x86.avx.storeu.dq.256(i8*, <32 x i8>) nounwind
2840 define void @test_x86_avx_storeu_pd_256(i8* %a0, <4 x double> %a1) {
2841 ; add operation forces the execution domain.
2842 ; CHECK-LABEL: test_x86_avx_storeu_pd_256:
2844 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2845 ; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1
2846 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
2847 ; CHECK-NEXT: vmovupd %ymm0, (%eax)
2848 ; CHECK-NEXT: vzeroupper
2850 %a2 = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
2851 call void @llvm.x86.avx.storeu.pd.256(i8* %a0, <4 x double> %a2)
2854 declare void @llvm.x86.avx.storeu.pd.256(i8*, <4 x double>) nounwind
2857 define void @test_x86_avx_storeu_ps_256(i8* %a0, <8 x float> %a1) {
2858 ; CHECK-LABEL: test_x86_avx_storeu_ps_256:
2860 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2861 ; CHECK-NEXT: vmovups %ymm0, (%eax)
2862 ; CHECK-NEXT: vzeroupper
2864 call void @llvm.x86.avx.storeu.ps.256(i8* %a0, <8 x float> %a1)
2867 declare void @llvm.x86.avx.storeu.ps.256(i8*, <8 x float>) nounwind
2870 define <4 x double> @test_x86_avx_vbroadcastf128_pd_256(i8* %a0) {
2871 ; CHECK-LABEL: test_x86_avx_vbroadcastf128_pd_256:
2873 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2874 ; CHECK-NEXT: vbroadcastf128 (%eax), %ymm0
2876 %res = call <4 x double> @llvm.x86.avx.vbroadcastf128.pd.256(i8* %a0) ; <<4 x double>> [#uses=1]
2877 ret <4 x double> %res
2879 declare <4 x double> @llvm.x86.avx.vbroadcastf128.pd.256(i8*) nounwind readonly
2882 define <8 x float> @test_x86_avx_vbroadcastf128_ps_256(i8* %a0) {
2883 ; CHECK-LABEL: test_x86_avx_vbroadcastf128_ps_256:
2885 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
2886 ; CHECK-NEXT: vbroadcastf128 (%eax), %ymm0
2888 %res = call <8 x float> @llvm.x86.avx.vbroadcastf128.ps.256(i8* %a0) ; <<8 x float>> [#uses=1]
2889 ret <8 x float> %res
2891 declare <8 x float> @llvm.x86.avx.vbroadcastf128.ps.256(i8*) nounwind readonly
2894 define <4 x double> @test_x86_avx_vperm2f128_pd_256(<4 x double> %a0, <4 x double> %a1) {
2895 ; CHECK-LABEL: test_x86_avx_vperm2f128_pd_256:
2897 ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1]
2899 %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1]
2900 ret <4 x double> %res
2902 declare <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
2905 define <8 x float> @test_x86_avx_vperm2f128_ps_256(<8 x float> %a0, <8 x float> %a1) {
2906 ; CHECK-LABEL: test_x86_avx_vperm2f128_ps_256:
2908 ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1]
2910 %res = call <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
2911 ret <8 x float> %res
2913 declare <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
2916 define <8 x i32> @test_x86_avx_vperm2f128_si_256(<8 x i32> %a0, <8 x i32> %a1) {
2917 ; CHECK-LABEL: test_x86_avx_vperm2f128_si_256:
2919 ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1]
2921 %res = call <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32> %a0, <8 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1]
2924 declare <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32>, <8 x i32>, i8) nounwind readnone
2927 define <2 x double> @test_x86_avx_vpermil_pd(<2 x double> %a0) {
2928 ; CHECK-LABEL: test_x86_avx_vpermil_pd:
2930 ; CHECK-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
2932 %res = call <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double> %a0, i8 1) ; <<2 x double>> [#uses=1]
2933 ret <2 x double> %res
2935 declare <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double>, i8) nounwind readnone
2938 define <4 x double> @test_x86_avx_vpermil_pd_256(<4 x double> %a0) {
2939 ; CHECK-LABEL: test_x86_avx_vpermil_pd_256:
2941 ; CHECK-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,2]
2943 %res = call <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double> %a0, i8 7) ; <<4 x double>> [#uses=1]
2944 ret <4 x double> %res
2946 declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8) nounwind readnone
2949 define <4 x float> @test_x86_avx_vpermil_ps(<4 x float> %a0) {
2950 ; CHECK-LABEL: test_x86_avx_vpermil_ps:
2952 ; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,0,0]
2954 %res = call <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float> %a0, i8 7) ; <<4 x float>> [#uses=1]
2955 ret <4 x float> %res
2957 declare <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float>, i8) nounwind readnone
2960 define <8 x float> @test_x86_avx_vpermil_ps_256(<8 x float> %a0) {
2961 ; CHECK-LABEL: test_x86_avx_vpermil_ps_256:
2963 ; CHECK-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,1,0,0,7,5,4,4]
2965 %res = call <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float> %a0, i8 7) ; <<8 x float>> [#uses=1]
2966 ret <8 x float> %res
2968 declare <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float>, i8) nounwind readnone
2971 define <2 x double> @test_x86_avx_vpermilvar_pd(<2 x double> %a0, <2 x i64> %a1) {
2972 ; CHECK-LABEL: test_x86_avx_vpermilvar_pd:
2974 ; CHECK-NEXT: vpermilpd %xmm1, %xmm0, %xmm0
2976 %res = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> %a1) ; <<2 x double>> [#uses=1]
2977 ret <2 x double> %res
2979 declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>) nounwind readnone
2982 define <4 x double> @test_x86_avx_vpermilvar_pd_256(<4 x double> %a0, <4 x i64> %a1) {
2983 ; CHECK-LABEL: test_x86_avx_vpermilvar_pd_256:
2985 ; CHECK-NEXT: vpermilpd %ymm1, %ymm0, %ymm0
2987 %res = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> %a1) ; <<4 x double>> [#uses=1]
2988 ret <4 x double> %res
2990 declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i64>) nounwind readnone
2992 define <4 x double> @test_x86_avx_vpermilvar_pd_256_2(<4 x double> %a0) {
2993 ; CHECK-LABEL: test_x86_avx_vpermilvar_pd_256_2:
2995 ; CHECK-NEXT: vpermilpd {{.*}}, %ymm0, %ymm0 ## ymm0 = ymm0[1,0,2,3]
2997 %res = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 2, i64 0, i64 0, i64 2>) ; <<4 x double>> [#uses=1]
2998 ret <4 x double> %res
3001 define <4 x float> @test_x86_avx_vpermilvar_ps(<4 x float> %a0, <4 x i32> %a1) {
3002 ; CHECK-LABEL: test_x86_avx_vpermilvar_ps:
3004 ; CHECK-NEXT: vpermilps %xmm1, %xmm0, %xmm0
3006 %res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a1) ; <<4 x float>> [#uses=1]
3007 ret <4 x float> %res
3009 define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, <4 x i32>* %a1) {
3010 ; CHECK-LABEL: test_x86_avx_vpermilvar_ps_load:
3012 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
3013 ; CHECK-NEXT: vpermilps (%eax), %xmm0, %xmm0
3015 %a2 = load <4 x i32>, <4 x i32>* %a1
3016 %res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a2) ; <<4 x float>> [#uses=1]
3017 ret <4 x float> %res
3019 declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) nounwind readnone
3022 define <8 x float> @test_x86_avx_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a1) {
3023 ; CHECK-LABEL: test_x86_avx_vpermilvar_ps_256:
3025 ; CHECK-NEXT: vpermilps %ymm1, %ymm0, %ymm0
3027 %res = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1]
3028 ret <8 x float> %res
3030 declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>) nounwind readnone
3033 define i32 @test_x86_avx_vtestc_pd(<2 x double> %a0, <2 x double> %a1) {
3034 ; CHECK-LABEL: test_x86_avx_vtestc_pd:
3036 ; CHECK-NEXT: vtestpd %xmm1, %xmm0
3037 ; CHECK-NEXT: sbbl %eax, %eax
3038 ; CHECK-NEXT: andl $1, %eax
3040 %res = call i32 @llvm.x86.avx.vtestc.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
3043 declare i32 @llvm.x86.avx.vtestc.pd(<2 x double>, <2 x double>) nounwind readnone
3046 define i32 @test_x86_avx_vtestc_pd_256(<4 x double> %a0, <4 x double> %a1) {
3047 ; CHECK-LABEL: test_x86_avx_vtestc_pd_256:
3049 ; CHECK-NEXT: vtestpd %ymm1, %ymm0
3050 ; CHECK-NEXT: sbbl %eax, %eax
3051 ; CHECK-NEXT: andl $1, %eax
3052 ; CHECK-NEXT: vzeroupper
3054 %res = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
3057 declare i32 @llvm.x86.avx.vtestc.pd.256(<4 x double>, <4 x double>) nounwind readnone
3060 define i32 @test_x86_avx_vtestc_ps(<4 x float> %a0, <4 x float> %a1) {
3061 ; CHECK-LABEL: test_x86_avx_vtestc_ps:
3063 ; CHECK-NEXT: vtestps %xmm1, %xmm0
3064 ; CHECK-NEXT: sbbl %eax, %eax
3065 ; CHECK-NEXT: andl $1, %eax
3067 %res = call i32 @llvm.x86.avx.vtestc.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
3070 declare i32 @llvm.x86.avx.vtestc.ps(<4 x float>, <4 x float>) nounwind readnone
3073 define i32 @test_x86_avx_vtestc_ps_256(<8 x float> %a0, <8 x float> %a1) {
3074 ; CHECK-LABEL: test_x86_avx_vtestc_ps_256:
3076 ; CHECK-NEXT: vtestps %ymm1, %ymm0
3077 ; CHECK-NEXT: sbbl %eax, %eax
3078 ; CHECK-NEXT: andl $1, %eax
3079 ; CHECK-NEXT: vzeroupper
3081 %res = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
3084 declare i32 @llvm.x86.avx.vtestc.ps.256(<8 x float>, <8 x float>) nounwind readnone
3087 define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) {
3088 ; CHECK-LABEL: test_x86_avx_vtestnzc_pd:
3090 ; CHECK-NEXT: vtestpd %xmm1, %xmm0
3091 ; CHECK-NEXT: seta %al
3092 ; CHECK-NEXT: movzbl %al, %eax
3094 %res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
3097 declare i32 @llvm.x86.avx.vtestnzc.pd(<2 x double>, <2 x double>) nounwind readnone
3100 define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) {
3101 ; CHECK-LABEL: test_x86_avx_vtestnzc_pd_256:
3103 ; CHECK-NEXT: vtestpd %ymm1, %ymm0
3104 ; CHECK-NEXT: seta %al
3105 ; CHECK-NEXT: movzbl %al, %eax
3106 ; CHECK-NEXT: vzeroupper
3108 %res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
3111 declare i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double>, <4 x double>) nounwind readnone
3114 define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) {
3115 ; CHECK-LABEL: test_x86_avx_vtestnzc_ps:
3117 ; CHECK-NEXT: vtestps %xmm1, %xmm0
3118 ; CHECK-NEXT: seta %al
3119 ; CHECK-NEXT: movzbl %al, %eax
3121 %res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
3124 declare i32 @llvm.x86.avx.vtestnzc.ps(<4 x float>, <4 x float>) nounwind readnone
3127 define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) {
3128 ; CHECK-LABEL: test_x86_avx_vtestnzc_ps_256:
3130 ; CHECK-NEXT: vtestps %ymm1, %ymm0
3131 ; CHECK-NEXT: seta %al
3132 ; CHECK-NEXT: movzbl %al, %eax
3133 ; CHECK-NEXT: vzeroupper
3135 %res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
3138 declare i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float>, <8 x float>) nounwind readnone
3141 define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) {
3142 ; CHECK-LABEL: test_x86_avx_vtestz_pd:
3144 ; CHECK-NEXT: vtestpd %xmm1, %xmm0
3145 ; CHECK-NEXT: sete %al
3146 ; CHECK-NEXT: movzbl %al, %eax
3148 %res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
3151 declare i32 @llvm.x86.avx.vtestz.pd(<2 x double>, <2 x double>) nounwind readnone
3154 define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) {
3155 ; CHECK-LABEL: test_x86_avx_vtestz_pd_256:
3157 ; CHECK-NEXT: vtestpd %ymm1, %ymm0
3158 ; CHECK-NEXT: sete %al
3159 ; CHECK-NEXT: movzbl %al, %eax
3160 ; CHECK-NEXT: vzeroupper
3162 %res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
3165 declare i32 @llvm.x86.avx.vtestz.pd.256(<4 x double>, <4 x double>) nounwind readnone
3168 define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) {
3169 ; CHECK-LABEL: test_x86_avx_vtestz_ps:
3171 ; CHECK-NEXT: vtestps %xmm1, %xmm0
3172 ; CHECK-NEXT: sete %al
3173 ; CHECK-NEXT: movzbl %al, %eax
3175 %res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
3178 declare i32 @llvm.x86.avx.vtestz.ps(<4 x float>, <4 x float>) nounwind readnone
3181 define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) {
3182 ; CHECK-LABEL: test_x86_avx_vtestz_ps_256:
3184 ; CHECK-NEXT: vtestps %ymm1, %ymm0
3185 ; CHECK-NEXT: sete %al
3186 ; CHECK-NEXT: movzbl %al, %eax
3187 ; CHECK-NEXT: vzeroupper
3189 %res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
3192 declare i32 @llvm.x86.avx.vtestz.ps.256(<8 x float>, <8 x float>) nounwind readnone
3195 define void @test_x86_avx_vzeroall() {
3196 ; CHECK-LABEL: test_x86_avx_vzeroall:
3198 ; CHECK-NEXT: vzeroall
3199 ; CHECK-NEXT: vzeroupper
3201 call void @llvm.x86.avx.vzeroall()
3204 declare void @llvm.x86.avx.vzeroall() nounwind
3207 define void @test_x86_avx_vzeroupper() {
3208 ; CHECK-LABEL: test_x86_avx_vzeroupper:
3210 ; CHECK-NEXT: vzeroupper
3211 ; CHECK-NEXT: vzeroupper
3213 call void @llvm.x86.avx.vzeroupper()
3216 declare void @llvm.x86.avx.vzeroupper() nounwind
3218 ; Make sure instructions with no AVX equivalents, but are associated with SSEX feature flags still work
3220 define void @monitor(i8* %P, i32 %E, i32 %H) nounwind {
3221 ; CHECK-LABEL: monitor:
3223 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
3224 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
3225 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
3226 ; CHECK-NEXT: leal (%eax), %eax
3227 ; CHECK-NEXT: monitor
3229 tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)
3232 declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
3234 define void @mwait(i32 %E, i32 %H) nounwind {
3235 ; CHECK-LABEL: mwait:
3237 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
3238 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
3241 tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)
3244 declare void @llvm.x86.sse3.mwait(i32, i32) nounwind
3246 define void @sfence() nounwind {
3247 ; CHECK-LABEL: sfence:
3249 ; CHECK-NEXT: sfence
3251 tail call void @llvm.x86.sse.sfence()
3254 declare void @llvm.x86.sse.sfence() nounwind
3256 define void @lfence() nounwind {
3257 ; CHECK-LABEL: lfence:
3259 ; CHECK-NEXT: lfence
3261 tail call void @llvm.x86.sse2.lfence()
3264 declare void @llvm.x86.sse2.lfence() nounwind
3266 define void @mfence() nounwind {
3267 ; CHECK-LABEL: mfence:
3269 ; CHECK-NEXT: mfence
3271 tail call void @llvm.x86.sse2.mfence()
3274 declare void @llvm.x86.sse2.mfence() nounwind
3276 define void @clflush(i8* %p) nounwind {
3277 ; CHECK-LABEL: clflush:
3279 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
3280 ; CHECK-NEXT: clflush (%eax)
3282 tail call void @llvm.x86.sse2.clflush(i8* %p)
3285 declare void @llvm.x86.sse2.clflush(i8*) nounwind
3287 define i32 @crc32_32_8(i32 %a, i8 %b) nounwind {
3288 ; CHECK-LABEL: crc32_32_8:
3290 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
3291 ; CHECK-NEXT: crc32b {{[0-9]+}}(%esp), %eax
3293 %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
3296 declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
3298 define i32 @crc32_32_16(i32 %a, i16 %b) nounwind {
3299 ; CHECK-LABEL: crc32_32_16:
3301 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
3302 ; CHECK-NEXT: crc32w {{[0-9]+}}(%esp), %eax
3304 %tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b)
3307 declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
3309 define i32 @crc32_32_32(i32 %a, i32 %b) nounwind {
3310 ; CHECK-LABEL: crc32_32_32:
3312 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
3313 ; CHECK-NEXT: crc32l {{[0-9]+}}(%esp), %eax
3315 %tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b)
3318 declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind
3320 define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind {
3321 ; CHECK-LABEL: movnt_dq:
3323 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
3324 ; CHECK-NEXT: vpaddq LCPI277_0, %xmm0, %xmm0
3325 ; CHECK-NEXT: vmovntdq %ymm0, (%eax)
3326 ; CHECK-NEXT: vzeroupper
3328 %a2 = add <2 x i64> %a1, <i64 1, i64 1>
3329 %a3 = shufflevector <2 x i64> %a2, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
3330 tail call void @llvm.x86.avx.movnt.dq.256(i8* %p, <4 x i64> %a3) nounwind
3333 declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind
3335 define void @movnt_ps(i8* %p, <8 x float> %a) nounwind {
3336 ; CHECK-LABEL: movnt_ps:
3338 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
3339 ; CHECK-NEXT: vmovntps %ymm0, (%eax)
3340 ; CHECK-NEXT: vzeroupper
3342 tail call void @llvm.x86.avx.movnt.ps.256(i8* %p, <8 x float> %a) nounwind
3345 declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind
3347 define void @movnt_pd(i8* %p, <4 x double> %a1) nounwind {
3348 ; add operation forces the execution domain.
3349 ; CHECK-LABEL: movnt_pd:
3351 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
3352 ; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1
3353 ; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0
3354 ; CHECK-NEXT: vmovntpd %ymm0, (%eax)
3355 ; CHECK-NEXT: vzeroupper
3357 %a2 = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
3358 tail call void @llvm.x86.avx.movnt.pd.256(i8* %p, <4 x double> %a2) nounwind
3361 declare void @llvm.x86.avx.movnt.pd.256(i8*, <4 x double>) nounwind
3364 ; Check for pclmulqdq
3365 define <2 x i64> @test_x86_pclmulqdq(<2 x i64> %a0, <2 x i64> %a1) {
3366 ; CHECK-LABEL: test_x86_pclmulqdq:
3368 ; CHECK-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0
3370 %res = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a0, <2 x i64> %a1, i8 0) ; <<2 x i64>> [#uses=1]
3373 declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8) nounwind readnone