1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
4 define <4 x float> @test1(<4 x float> %a) nounwind {
5 %b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef>
13 define <3 x i64> @test2(<2 x i64> %v) nounwind readnone {
16 %1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef>
17 %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2>
22 define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
23 %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 undef>
30 define <8 x float> @test4(float %a) nounwind {
31 %b = insertelement <8 x float> zeroinitializer, float %a, i32 0
38 define <8 x float> @test5(float* nocapture %f) nounwind uwtable readonly ssp {
40 %0 = bitcast float* %f to <4 x float>*
41 %1 = load <4 x float>* %0, align 16
45 ; CHECK-NOT: vinsertf128
46 %shuffle.i = shufflevector <4 x float> %1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
47 ret <8 x float> %shuffle.i
50 define <4 x double> @test6(double* nocapture %d) nounwind uwtable readonly ssp {
52 %0 = bitcast double* %d to <2 x double>*
53 %1 = load <2 x double>* %0, align 16
57 ; CHECK-NOT: vinsertf128
58 %shuffle.i = shufflevector <2 x double> %1, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
59 ret <4 x double> %shuffle.i
62 define <16 x i16> @test7(<4 x i16> %a) nounwind {
64 %b = shufflevector <4 x i16> %a, <4 x i16> undef, <16 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
70 define void @test8() {
72 %0 = load <16 x i64> addrspace(1)* null, align 128
73 %1 = shufflevector <16 x i64> <i64 undef, i64 undef, i64 0, i64 undef, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 undef, i64 0, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i64> %0, <16 x i32> <i32 17, i32 18, i32 2, i32 undef, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 undef, i32 11, i32 undef, i32 undef, i32 undef, i32 26>
74 %2 = shufflevector <16 x i64> %1, <16 x i64> %0, <16 x i32> <i32 0, i32 1, i32 2, i32 30, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 undef, i32 11, i32 undef, i32 22, i32 20, i32 15>
75 store <16 x i64> %2, <16 x i64> addrspace(1)* undef, align 128
80 ; Extract a value from a shufflevector..
81 define i32 @test9(<4 x i32> %a) nounwind {
84 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 undef, i32 4>
85 %r = extractelement <8 x i32> %b, i32 2
90 ; Extract a value which is the result of an undef mask.
91 define i32 @test10(<4 x i32> %a) nounwind {
93 ; CHECK-NOT: {{^[^#]*[a-z]}}
95 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
96 %r = extractelement <8 x i32> %b, i32 2
100 define <4 x float> @test11(<4 x float> %a) nounwind {
103 %tmp1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
104 ret <4 x float> %tmp1
107 define <4 x float> @test12(<4 x float>* %a) nounwind {
110 %tmp0 = load <4 x float>* %a
111 %tmp1 = shufflevector <4 x float> %tmp0, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
112 ret <4 x float> %tmp1
115 define <4 x i32> @test13(<4 x i32> %a) nounwind {
118 %tmp1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
122 define <4 x i32> @test14(<4 x i32>* %a) nounwind {
124 ; CHECK: vpshufd $27, (
125 %tmp0 = load <4 x i32>* %a
126 %tmp1 = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
133 define <4 x i32> @test15(<2 x i32>%x) nounwind readnone {
134 %x1 = shufflevector <2 x i32> %x, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
139 define <8 x float> @test16(float* nocapture %f) nounwind uwtable readonly ssp {
141 %0 = bitcast float* %f to <4 x float>*
142 %1 = load <4 x float>* %0, align 8
146 ; CHECK-NOT: vinsertf128
147 %shuffle.i = shufflevector <4 x float> %1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
148 ret <8 x float> %shuffle.i
157 define <32 x i8> @shuf1(<32 x i8> %inval1, <32 x i8> %inval2) {
159 %0 = shufflevector <32 x i8> %inval1, <32 x i8> %inval2, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62>
163 ; handle the case where only half of the 256-bits is splittable
169 define <32 x i8> @shuf2(<32 x i8> %inval1, <32 x i8> %inval2) {
171 %0 = shufflevector <32 x i8> %inval1, <32 x i8> %inval2, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 31, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62>
178 define <4 x i32> @blend1(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
179 %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
186 define <4 x i32> @blend2(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
187 %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
194 define <4 x float> @blend2a(<4 x float> %a, <4 x float> %b) nounwind alwaysinline {
195 %t = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
200 ; CHECK-NOT: vblendps
202 define <4 x i32> @blend3(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
203 %t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 2, i32 7>
210 define <4 x i64> @blend4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline {
211 %t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
218 define <16 x i16> @narrow(<16 x i16> %a) nounwind alwaysinline {
219 %t = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 1, i32 6, i32 7, i32 4, i32 5, i32 10, i32 11, i32 8, i32 undef, i32 14, i32 15, i32 undef, i32 undef>
223 ;CHECK-LABEL: test17:
224 ;CHECK-NOT: vinsertf128
226 define <8 x float> @test17(<4 x float> %y) {
227 %x = shufflevector <4 x float> %y, <4 x float> undef, <8 x i32> <i32 undef, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
235 define <8 x float> @test18(<8 x float> %A, <8 x float>%B) nounwind {
236 %S = shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
244 define <8 x float> @test19(<8 x float> %A, <8 x float>%B) nounwind {
245 %S = shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
250 ; Make sure loads happen before stores.
251 ; CHECK: swap8doubles
252 ; CHECK: vmovups {{[0-9]*}}(%rdi), %xmm{{[0-9]+}}
253 ; CHECK: vmovups {{[0-9]*}}(%rdi), %xmm{{[0-9]+}}
254 ; CHECK: vinsertf128 $1, {{[0-9]*}}(%rdi), %ymm{{[0-9]+}}
255 ; CHECK: vinsertf128 $1, {{[0-9]*}}(%rdi), %ymm{{[0-9]+}}
256 ; CHECK: vmovaps {{[0-9]*}}(%rsi), %ymm{{[0-9]+}}
257 ; CHECK: vmovaps {{[0-9]*}}(%rsi), %ymm{{[0-9]+}}
258 ; CHECK: vmovaps %xmm{{[0-9]+}}, {{[0-9]*}}(%rdi)
259 ; CHECK: vextractf128
260 ; CHECK: vmovaps %xmm{{[0-9]+}}, {{[0-9]*}}(%rdi)
261 ; CHECK: vextractf128
262 ; CHECK: vmovaps %ymm{{[0-9]+}}, {{[0-9]*}}(%rsi)
263 ; CHECK: vmovaps %ymm{{[0-9]+}}, {{[0-9]*}}(%rsi)
264 define void @swap8doubles(double* nocapture %A, double* nocapture %C) nounwind uwtable ssp {
266 %add.ptr = getelementptr inbounds double* %A, i64 2
267 %v.i = bitcast double* %A to <2 x double>*
268 %0 = load <2 x double>* %v.i, align 1
269 %shuffle.i.i = shufflevector <2 x double> %0, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
270 %v1.i = bitcast double* %add.ptr to <2 x double>*
271 %1 = load <2 x double>* %v1.i, align 1
272 %2 = tail call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %shuffle.i.i, <2 x double> %1, i8 1) nounwind
273 %add.ptr1 = getelementptr inbounds double* %A, i64 6
274 %add.ptr2 = getelementptr inbounds double* %A, i64 4
275 %v.i27 = bitcast double* %add.ptr2 to <2 x double>*
276 %3 = load <2 x double>* %v.i27, align 1
277 %shuffle.i.i28 = shufflevector <2 x double> %3, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
278 %v1.i29 = bitcast double* %add.ptr1 to <2 x double>*
279 %4 = load <2 x double>* %v1.i29, align 1
280 %5 = tail call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %shuffle.i.i28, <2 x double> %4, i8 1) nounwind
281 %6 = bitcast double* %C to <4 x double>*
282 %7 = load <4 x double>* %6, align 32
283 %add.ptr5 = getelementptr inbounds double* %C, i64 4
284 %8 = bitcast double* %add.ptr5 to <4 x double>*
285 %9 = load <4 x double>* %8, align 32
286 %shuffle.i26 = shufflevector <4 x double> %7, <4 x double> undef, <2 x i32> <i32 0, i32 1>
287 %10 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %7, i8 1)
288 %shuffle.i = shufflevector <4 x double> %9, <4 x double> undef, <2 x i32> <i32 0, i32 1>
289 %11 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %9, i8 1)
290 store <2 x double> %shuffle.i26, <2 x double>* %v.i, align 16
291 store <2 x double> %10, <2 x double>* %v1.i, align 16
292 store <2 x double> %shuffle.i, <2 x double>* %v.i27, align 16
293 store <2 x double> %11, <2 x double>* %v1.i29, align 16
294 store <4 x double> %2, <4 x double>* %6, align 32
295 store <4 x double> %5, <4 x double>* %8, align 32
298 declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
299 declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
301 ; this test case just should not fail
302 define void @test20() {
303 %a0 = insertelement <3 x double> <double 0.000000e+00, double 0.000000e+00, double undef>, double 0.000000e+00, i32 2
304 store <3 x double> %a0, <3 x double>* undef, align 1
305 %a1 = insertelement <3 x double> <double 0.000000e+00, double 0.000000e+00, double undef>, double undef, i32 2
306 store <3 x double> %a1, <3 x double>* undef, align 1
310 define <2 x i64> @test_insert_64_zext(<2 x i64> %i) {
311 ; CHECK-LABEL: test_insert_64_zext
314 %1 = shufflevector <2 x i64> %i, <2 x i64> <i64 0, i64 undef>, <2 x i32> <i32 0, i32 2>
318 ;; Ensure we don't use insertps from non v4x32 vectors.
319 ;; On SSE4.1 it works because bigger vectors use more than 1 register.
320 ;; On AVX they get passed in a single register.
321 ;; FIXME: We could probably optimize this case, if we're only using the
323 define <4 x i32> @insert_from_diff_size(<8 x i32> %x) {
324 ; CHECK-LABEL: insert_from_diff_size:
325 ; CHECK-NOT: insertps
327 %vecext = extractelement <8 x i32> %x, i32 0
328 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
329 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
330 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
331 %a.0 = extractelement <8 x i32> %x, i32 0
332 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %a.0, i32 3
333 ret <4 x i32> %vecinit3