1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+avx2 | FileCheck %s
3 define <16 x i16> @test_lvm_x86_avx2_pmovsxbw(<16 x i8>* %a) {
4 ; CHECK-LABEL: test_lvm_x86_avx2_pmovsxbw
5 ; CHECK: vpmovsxbw (%rdi), %ymm0
6 %1 = load <16 x i8>* %a, align 1
7 %2 = call <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8> %1)
11 define <8 x i32> @test_llvm_x86_avx2_pmovsxbd(<16 x i8>* %a) {
12 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxbd
13 ; CHECK: vpmovsxbd (%rdi), %ymm0
14 %1 = load <16 x i8>* %a, align 1
15 %2 = call <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8> %1)
19 define <4 x i64> @test_llvm_x86_avx2_pmovsxbq(<16 x i8>* %a) {
20 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxbq
21 ; CHECK: vpmovsxbq (%rdi), %ymm0
22 %1 = load <16 x i8>* %a, align 1
23 %2 = call <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8> %1)
27 define <8 x i32> @test_llvm_x86_avx2_pmovsxwd(<8 x i16>* %a) {
28 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxwd
29 ; CHECK: vpmovsxwd (%rdi), %ymm0
30 %1 = load <8 x i16>* %a, align 1
31 %2 = call <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16> %1)
35 define <4 x i64> @test_llvm_x86_avx2_pmovsxwq(<8 x i16>* %a) {
36 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxwq
37 ; CHECK: vpmovsxwq (%rdi), %ymm0
38 %1 = load <8 x i16>* %a, align 1
39 %2 = call <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16> %1)
43 define <4 x i64> @test_llvm_x86_avx2_pmovsxdq(<4 x i32>* %a) {
44 ; CHECK-LABEL: test_llvm_x86_avx2_pmovsxdq
45 ; CHECK: vpmovsxdq (%rdi), %ymm0
46 %1 = load <4 x i32>* %a, align 1
47 %2 = call <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32> %1)
51 define <16 x i16> @test_lvm_x86_avx2_pmovzxbw(<16 x i8>* %a) {
52 ; CHECK-LABEL: test_lvm_x86_avx2_pmovzxbw
53 ; CHECK: vpmovzxbw (%rdi), %ymm0
54 %1 = load <16 x i8>* %a, align 1
55 %2 = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %1)
59 define <8 x i32> @test_llvm_x86_avx2_pmovzxbd(<16 x i8>* %a) {
60 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxbd
61 ; CHECK: vpmovzxbd (%rdi), %ymm0
62 %1 = load <16 x i8>* %a, align 1
63 %2 = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %1)
67 define <4 x i64> @test_llvm_x86_avx2_pmovzxbq(<16 x i8>* %a) {
68 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxbq
69 ; CHECK: vpmovzxbq (%rdi), %ymm0
70 %1 = load <16 x i8>* %a, align 1
71 %2 = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %1)
75 define <8 x i32> @test_llvm_x86_avx2_pmovzxwd(<8 x i16>* %a) {
76 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxwd
77 ; CHECK: vpmovzxwd (%rdi), %ymm0
78 %1 = load <8 x i16>* %a, align 1
79 %2 = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %1)
83 define <4 x i64> @test_llvm_x86_avx2_pmovzxwq(<8 x i16>* %a) {
84 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxwq
85 ; CHECK: vpmovzxwq (%rdi), %ymm0
86 %1 = load <8 x i16>* %a, align 1
87 %2 = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %1)
91 define <4 x i64> @test_llvm_x86_avx2_pmovzxdq(<4 x i32>* %a) {
92 ; CHECK-LABEL: test_llvm_x86_avx2_pmovzxdq
93 ; CHECK: vpmovzxdq (%rdi), %ymm0
94 %1 = load <4 x i32>* %a, align 1
95 %2 = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %1)
99 declare <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32>)
100 declare <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16>)
101 declare <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16>)
102 declare <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8>)
103 declare <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8>)
104 declare <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8>)
105 declare <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32>)
106 declare <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16>)
107 declare <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16>)
108 declare <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8>)
109 declare <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8>)
110 declare <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8>)