1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
3 ; AVX2 Logical Shift Left
5 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
7 %shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
11 ; CHECK-LABEL: test_sllw_1:
12 ; CHECK: vpsllw $0, %ymm0, %ymm0
15 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
17 %shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
21 ; CHECK-LABEL: test_sllw_2:
22 ; CHECK: vpaddw %ymm0, %ymm0, %ymm0
25 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
27 %shl = shl <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
31 ; CHECK-LABEL: test_sllw_3:
32 ; CHECK: vxorps %ymm0, %ymm0, %ymm0
35 define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
37 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
41 ; CHECK-LABEL: test_slld_1:
42 ; CHECK: vpslld $0, %ymm0, %ymm0
45 define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
47 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
51 ; CHECK-LABEL: test_slld_2:
52 ; CHECK: vpaddd %ymm0, %ymm0, %ymm0
55 define <8 x i32> @test_slld_3(<8 x i32> %InVec) {
57 %shl = shl <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
61 ; CHECK-LABEL: test_slld_3:
62 ; CHECK: vxorps %ymm0, %ymm0, %ymm0
65 define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {
67 %shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
71 ; CHECK-LABEL: test_sllq_1:
72 ; CHECK: vpsllq $0, %ymm0, %ymm0
75 define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {
77 %shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
81 ; CHECK-LABEL: test_sllq_2:
82 ; CHECK: vpaddq %ymm0, %ymm0, %ymm0
85 define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {
87 %shl = shl <4 x i64> %InVec, <i64 64, i64 64, i64 64, i64 64>
91 ; CHECK-LABEL: test_sllq_3:
92 ; CHECK: vxorps %ymm0, %ymm0, %ymm0
95 ; AVX2 Arithmetic Shift
97 define <16 x i16> @test_sraw_1(<16 x i16> %InVec) {
99 %shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
103 ; CHECK-LABEL: test_sraw_1:
104 ; CHECK: vpsraw $0, %ymm0, %ymm0
107 define <16 x i16> @test_sraw_2(<16 x i16> %InVec) {
109 %shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
113 ; CHECK-LABEL: test_sraw_2:
114 ; CHECK: vpsraw $1, %ymm0, %ymm0
117 define <16 x i16> @test_sraw_3(<16 x i16> %InVec) {
119 %shl = ashr <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
123 ; CHECK-LABEL: test_sraw_3:
124 ; CHECK: vpsraw $16, %ymm0, %ymm0
127 define <8 x i32> @test_srad_1(<8 x i32> %InVec) {
129 %shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
133 ; CHECK-LABEL: test_srad_1:
134 ; CHECK: vpsrad $0, %ymm0, %ymm0
137 define <8 x i32> @test_srad_2(<8 x i32> %InVec) {
139 %shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
143 ; CHECK-LABEL: test_srad_2:
144 ; CHECK: vpsrad $1, %ymm0, %ymm0
147 define <8 x i32> @test_srad_3(<8 x i32> %InVec) {
149 %shl = ashr <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
153 ; CHECK-LABEL: test_srad_3:
154 ; CHECK: vpsrad $32, %ymm0, %ymm0
157 ; SSE Logical Shift Right
159 define <16 x i16> @test_srlw_1(<16 x i16> %InVec) {
161 %shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
165 ; CHECK-LABEL: test_srlw_1:
166 ; CHECK: vpsrlw $0, %ymm0, %ymm0
169 define <16 x i16> @test_srlw_2(<16 x i16> %InVec) {
171 %shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
175 ; CHECK-LABEL: test_srlw_2:
176 ; CHECK: vpsrlw $1, %ymm0, %ymm0
179 define <16 x i16> @test_srlw_3(<16 x i16> %InVec) {
181 %shl = lshr <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
185 ; CHECK-LABEL: test_srlw_3:
186 ; CHECK: vxorps %ymm0, %ymm0, %ymm0
189 define <8 x i32> @test_srld_1(<8 x i32> %InVec) {
191 %shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
195 ; CHECK-LABEL: test_srld_1:
196 ; CHECK: vpsrld $0, %ymm0, %ymm0
199 define <8 x i32> @test_srld_2(<8 x i32> %InVec) {
201 %shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
205 ; CHECK-LABEL: test_srld_2:
206 ; CHECK: vpsrld $1, %ymm0, %ymm0
209 define <8 x i32> @test_srld_3(<8 x i32> %InVec) {
211 %shl = lshr <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
215 ; CHECK-LABEL: test_srld_3:
216 ; CHECK: vxorps %ymm0, %ymm0, %ymm0
219 define <4 x i64> @test_srlq_1(<4 x i64> %InVec) {
221 %shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
225 ; CHECK-LABEL: test_srlq_1:
226 ; CHECK: vpsrlq $0, %ymm0, %ymm0
229 define <4 x i64> @test_srlq_2(<4 x i64> %InVec) {
231 %shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
235 ; CHECK-LABEL: test_srlq_2:
236 ; CHECK: vpsrlq $1, %ymm0, %ymm0
239 define <4 x i64> @test_srlq_3(<4 x i64> %InVec) {
241 %shl = lshr <4 x i64> %InVec, <i64 64, i64 64, i64 64, i64 64>
245 ; CHECK-LABEL: test_srlq_3:
246 ; CHECK: vxorps %ymm0, %ymm0, %ymm0