1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
3 ; AVX2 Logical Shift Left
5 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
7 %shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
11 ; CHECK-LABEL: test_sllw_1:
12 ; CHECK-NOT: vpsllw $0, %ymm0, %ymm0
15 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
17 %shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
21 ; CHECK-LABEL: test_sllw_2:
22 ; CHECK: vpaddw %ymm0, %ymm0, %ymm0
25 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
27 %shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
31 ; CHECK-LABEL: test_sllw_3:
32 ; CHECK: vpsllw $15, %ymm0, %ymm0
35 define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
37 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
41 ; CHECK-LABEL: test_slld_1:
42 ; CHECK-NOT: vpslld $0, %ymm0, %ymm0
45 define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
47 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
51 ; CHECK-LABEL: test_slld_2:
52 ; CHECK: vpaddd %ymm0, %ymm0, %ymm0
55 define <8 x i32> @test_vpslld_var(i32 %shift) {
56 %amt = insertelement <8 x i32> undef, i32 %shift, i32 0
57 %tmp = shl <8 x i32> <i32 192, i32 193, i32 194, i32 195, i32 196, i32 197, i32 198, i32 199>, %amt
61 ; CHECK-LABEL: test_vpslld_var:
62 ; CHECK: vpslld %xmm0, %ymm1, %ymm0
65 define <8 x i32> @test_slld_3(<8 x i32> %InVec) {
67 %shl = shl <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
71 ; CHECK-LABEL: test_slld_3:
72 ; CHECK: vpslld $31, %ymm0, %ymm0
75 define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {
77 %shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
81 ; CHECK-LABEL: test_sllq_1:
82 ; CHECK-NOT: vpsllq $0, %ymm0, %ymm0
85 define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {
87 %shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
91 ; CHECK-LABEL: test_sllq_2:
92 ; CHECK: vpaddq %ymm0, %ymm0, %ymm0
95 define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {
97 %shl = shl <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>
101 ; CHECK-LABEL: test_sllq_3:
102 ; CHECK: vpsllq $63, %ymm0, %ymm0
105 ; AVX2 Arithmetic Shift
107 define <16 x i16> @test_sraw_1(<16 x i16> %InVec) {
109 %shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
113 ; CHECK-LABEL: test_sraw_1:
114 ; CHECK-NOT: vpsraw $0, %ymm0, %ymm0
117 define <16 x i16> @test_sraw_2(<16 x i16> %InVec) {
119 %shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
123 ; CHECK-LABEL: test_sraw_2:
124 ; CHECK: vpsraw $1, %ymm0, %ymm0
127 define <16 x i16> @test_sraw_3(<16 x i16> %InVec) {
129 %shl = ashr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
133 ; CHECK-LABEL: test_sraw_3:
134 ; CHECK: vpsraw $15, %ymm0, %ymm0
137 define <8 x i32> @test_srad_1(<8 x i32> %InVec) {
139 %shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
143 ; CHECK-LABEL: test_srad_1:
144 ; CHECK-NOT: vpsrad $0, %ymm0, %ymm0
147 define <8 x i32> @test_srad_2(<8 x i32> %InVec) {
149 %shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
153 ; CHECK-LABEL: test_srad_2:
154 ; CHECK: vpsrad $1, %ymm0, %ymm0
157 define <8 x i32> @test_srad_3(<8 x i32> %InVec) {
159 %shl = ashr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
163 ; CHECK-LABEL: test_srad_3:
164 ; CHECK: vpsrad $31, %ymm0, %ymm0
167 ; SSE Logical Shift Right
169 define <16 x i16> @test_srlw_1(<16 x i16> %InVec) {
171 %shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
175 ; CHECK-LABEL: test_srlw_1:
176 ; CHECK-NOT: vpsrlw $0, %ymm0, %ymm0
179 define <16 x i16> @test_srlw_2(<16 x i16> %InVec) {
181 %shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
185 ; CHECK-LABEL: test_srlw_2:
186 ; CHECK: vpsrlw $1, %ymm0, %ymm0
189 define <16 x i16> @test_srlw_3(<16 x i16> %InVec) {
191 %shl = lshr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
195 ; CHECK-LABEL: test_srlw_3:
196 ; CHECK: vpsrlw $15, %ymm0, %ymm0
199 define <8 x i32> @test_srld_1(<8 x i32> %InVec) {
201 %shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
205 ; CHECK-LABEL: test_srld_1:
206 ; CHECK-NOT: vpsrld $0, %ymm0, %ymm0
209 define <8 x i32> @test_srld_2(<8 x i32> %InVec) {
211 %shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
215 ; CHECK-LABEL: test_srld_2:
216 ; CHECK: vpsrld $1, %ymm0, %ymm0
219 define <8 x i32> @test_srld_3(<8 x i32> %InVec) {
221 %shl = lshr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
225 ; CHECK-LABEL: test_srld_3:
226 ; CHECK: vpsrld $31, %ymm0, %ymm0
229 define <4 x i64> @test_srlq_1(<4 x i64> %InVec) {
231 %shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
235 ; CHECK-LABEL: test_srlq_1:
236 ; CHECK-NOT: vpsrlq $0, %ymm0, %ymm0
239 define <4 x i64> @test_srlq_2(<4 x i64> %InVec) {
241 %shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
245 ; CHECK-LABEL: test_srlq_2:
246 ; CHECK: vpsrlq $1, %ymm0, %ymm0
249 define <4 x i64> @test_srlq_3(<4 x i64> %InVec) {
251 %shl = lshr <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>
255 ; CHECK-LABEL: test_srlq_3:
256 ; CHECK: vpsrlq $63, %ymm0, %ymm0
259 ; CHECK-LABEL: @srl_trunc_and_v4i64
261 ; CHECK-NEXT: vpsrlvd
263 define <4 x i32> @srl_trunc_and_v4i64(<4 x i32> %x, <4 x i64> %y) nounwind {
264 %and = and <4 x i64> %y, <i64 8, i64 8, i64 8, i64 8>
265 %trunc = trunc <4 x i64> %and to <4 x i32>
266 %sra = lshr <4 x i32> %x, %trunc
271 ; Vectorized byte shifts
274 define <8 x i16> @shl_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {
275 ; CHECK-LABEL: shl_8i16
276 ; CHECK: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
277 ; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
278 ; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
279 ; CHECK-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero
280 ; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
282 %shl = shl <8 x i16> %r, %a
286 define <16 x i16> @shl_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {
287 ; CHECK-LABEL: shl_16i16
288 ; CHECK: vpxor %ymm2, %ymm2, %ymm2
289 ; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
290 ; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15]
291 ; CHECK-NEXT: vpsllvd %ymm3, %ymm4, %ymm3
292 ; CHECK-NEXT: vpsrld $16, %ymm3, %ymm3
293 ; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
294 ; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11]
295 ; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
296 ; CHECK-NEXT: vpsrld $16, %ymm0, %ymm0
297 ; CHECK-NEXT: vpackusdw %ymm3, %ymm0, %ymm0
299 %shl = shl <16 x i16> %r, %a
303 define <32 x i8> @shl_32i8(<32 x i8> %r, <32 x i8> %a) nounwind {
304 ; CHECK-LABEL: shl_32i8
305 ; CHECK: vextracti128 $1, %ymm0, %xmm3
306 ; CHECK-NEXT: vpsllw $4, %xmm3, %xmm2
307 ; CHECK-NEXT: vmovdqa {{.*#+}} xmm8 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
308 ; CHECK-NEXT: vpand %xmm8, %xmm2, %xmm5
309 ; CHECK-NEXT: vextracti128 $1, %ymm1, %xmm2
310 ; CHECK-NEXT: vpsllw $5, %xmm2, %xmm2
311 ; CHECK-NEXT: vmovdqa {{.*#+}} xmm9 = [224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224]
312 ; CHECK-NEXT: vpand %xmm9, %xmm2, %xmm7
313 ; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
314 ; CHECK-NEXT: vpand %xmm7, %xmm2, %xmm4
315 ; CHECK-NEXT: vpcmpeqb %xmm2, %xmm4, %xmm4
316 ; CHECK-NEXT: vpblendvb %xmm4, %xmm5, %xmm3, %xmm3
317 ; CHECK-NEXT: vpsllw $2, %xmm3, %xmm4
318 ; CHECK-NEXT: vmovdqa {{.*#+}} xmm5 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
319 ; CHECK-NEXT: vpand %xmm5, %xmm4, %xmm4
320 ; CHECK-NEXT: vpaddb %xmm7, %xmm7, %xmm7
321 ; CHECK-NEXT: vpand %xmm7, %xmm2, %xmm6
322 ; CHECK-NEXT: vpcmpeqb %xmm2, %xmm6, %xmm6
323 ; CHECK-NEXT: vpblendvb %xmm6, %xmm4, %xmm3, %xmm3
324 ; CHECK-NEXT: vpaddb %xmm3, %xmm3, %xmm4
325 ; CHECK-NEXT: vpaddb %xmm7, %xmm7, %xmm6
326 ; CHECK-NEXT: vpand %xmm6, %xmm2, %xmm6
327 ; CHECK-NEXT: vpcmpeqb %xmm2, %xmm6, %xmm6
328 ; CHECK-NEXT: vpblendvb %xmm6, %xmm4, %xmm3, %xmm3
329 ; CHECK-NEXT: vpsllw $4, %xmm0, %xmm4
330 ; CHECK-NEXT: vpand %xmm8, %xmm4, %xmm4
331 ; CHECK-NEXT: vpsllw $5, %xmm1, %xmm1
332 ; CHECK-NEXT: vpand %xmm9, %xmm1, %xmm1
333 ; CHECK-NEXT: vpand %xmm1, %xmm2, %xmm6
334 ; CHECK-NEXT: vpcmpeqb %xmm2, %xmm6, %xmm6
335 ; CHECK-NEXT: vpblendvb %xmm6, %xmm4, %xmm0, %xmm0
336 ; CHECK-NEXT: vpsllw $2, %xmm0, %xmm4
337 ; CHECK-NEXT: vpand %xmm5, %xmm4, %xmm4
338 ; CHECK-NEXT: vpaddb %xmm1, %xmm1, %xmm1
339 ; CHECK-NEXT: vpand %xmm1, %xmm2, %xmm5
340 ; CHECK-NEXT: vpcmpeqb %xmm2, %xmm5, %xmm5
341 ; CHECK-NEXT: vpblendvb %xmm5, %xmm4, %xmm0, %xmm0
342 ; CHECK-NEXT: vpaddb %xmm0, %xmm0, %xmm4
343 ; CHECK-NEXT: vpaddb %xmm1, %xmm1, %xmm1
344 ; CHECK-NEXT: vpand %xmm1, %xmm2, %xmm1
345 ; CHECK-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1
346 ; CHECK-NEXT: vpblendvb %xmm1, %xmm4, %xmm0, %xmm0
347 ; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
349 %shl = shl <32 x i8> %r, %a
353 define <8 x i16> @ashr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {
354 ; CHECK-LABEL: ashr_8i16
355 ; CHECK: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
356 ; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0
357 ; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm0
358 ; CHECK-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero
359 ; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
361 %ashr = ashr <8 x i16> %r, %a
365 define <16 x i16> @ashr_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {
366 ; CHECK-LABEL: ashr_16i16
367 ; CHECK: vpxor %ymm2, %ymm2, %ymm2
368 ; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
369 ; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15]
370 ; CHECK-NEXT: vpsravd %ymm3, %ymm4, %ymm3
371 ; CHECK-NEXT: vpsrld $16, %ymm3, %ymm3
372 ; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
373 ; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11]
374 ; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm0
375 ; CHECK-NEXT: vpsrld $16, %ymm0, %ymm0
376 ; CHECK-NEXT: vpackusdw %ymm3, %ymm0, %ymm0
378 %ashr = ashr <16 x i16> %r, %a
382 define <32 x i8> @ashr_32i8(<32 x i8> %r, <32 x i8> %a) nounwind {
383 ; CHECK-LABEL: ashr_32i8
384 ; CHECK: vextracti128 $1, %ymm1, %xmm2
385 ; CHECK-NEXT: vpextrb $1, %xmm2, %ecx
386 ; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm3
387 ; CHECK-NEXT: vpextrb $1, %xmm3, %eax
388 ; CHECK-NEXT: sarb %cl, %al
389 ; CHECK-NEXT: vpextrb $0, %xmm2, %ecx
390 ; CHECK-NEXT: vpextrb $0, %xmm3, %edx
391 ; CHECK-NEXT: sarb %cl, %dl
392 ; CHECK-NEXT: movzbl %al, %eax
393 ; CHECK-NEXT: movzbl %dl, %edx
394 ; CHECK-NEXT: vpextrb $2, %xmm2, %ecx
395 ; CHECK-NEXT: vpextrb $2, %xmm3, %esi
396 ; CHECK-NEXT: sarb %cl, %sil
397 ; CHECK-NEXT: vmovd %edx, %xmm4
398 ; CHECK-NEXT: vpinsrb $1, %eax, %xmm4, %xmm4
399 ; CHECK-NEXT: movzbl %sil, %eax
400 ; CHECK-NEXT: vpextrb $3, %xmm2, %ecx
401 ; CHECK-NEXT: vpextrb $3, %xmm3, %edx
402 ; CHECK-NEXT: sarb %cl, %dl
403 ; CHECK-NEXT: vpinsrb $2, %eax, %xmm4, %xmm4
404 ; CHECK-NEXT: movzbl %dl, %eax
405 ; CHECK-NEXT: vpinsrb $3, %eax, %xmm4, %xmm4
406 ; CHECK-NEXT: vpextrb $4, %xmm2, %ecx
407 ; CHECK-NEXT: vpextrb $4, %xmm3, %eax
408 ; CHECK-NEXT: sarb %cl, %al
409 ; CHECK-NEXT: movzbl %al, %eax
410 ; CHECK-NEXT: vpinsrb $4, %eax, %xmm4, %xmm4
411 ; CHECK-NEXT: vpextrb $5, %xmm2, %ecx
412 ; CHECK-NEXT: vpextrb $5, %xmm3, %eax
413 ; CHECK-NEXT: sarb %cl, %al
414 ; CHECK-NEXT: vpextrb $6, %xmm2, %ecx
415 ; CHECK-NEXT: vpextrb $6, %xmm3, %edx
416 ; CHECK-NEXT: sarb %cl, %dl
417 ; CHECK-NEXT: movzbl %al, %eax
418 ; CHECK-NEXT: vpinsrb $5, %eax, %xmm4, %xmm4
419 ; CHECK-NEXT: movzbl %dl, %eax
420 ; CHECK-NEXT: vpextrb $7, %xmm2, %ecx
421 ; CHECK-NEXT: vpextrb $7, %xmm3, %edx
422 ; CHECK-NEXT: sarb %cl, %dl
423 ; CHECK-NEXT: vpinsrb $6, %eax, %xmm4, %xmm4
424 ; CHECK-NEXT: movzbl %dl, %eax
425 ; CHECK-NEXT: vpinsrb $7, %eax, %xmm4, %xmm4
426 ; CHECK-NEXT: vpextrb $8, %xmm2, %ecx
427 ; CHECK-NEXT: vpextrb $8, %xmm3, %eax
428 ; CHECK-NEXT: sarb %cl, %al
429 ; CHECK-NEXT: movzbl %al, %eax
430 ; CHECK-NEXT: vpinsrb $8, %eax, %xmm4, %xmm4
431 ; CHECK-NEXT: vpextrb $9, %xmm2, %ecx
432 ; CHECK-NEXT: vpextrb $9, %xmm3, %eax
433 ; CHECK-NEXT: sarb %cl, %al
434 ; CHECK-NEXT: vpextrb $10, %xmm2, %ecx
435 ; CHECK-NEXT: vpextrb $10, %xmm3, %edx
436 ; CHECK-NEXT: sarb %cl, %dl
437 ; CHECK-NEXT: movzbl %al, %eax
438 ; CHECK-NEXT: vpinsrb $9, %eax, %xmm4, %xmm4
439 ; CHECK-NEXT: movzbl %dl, %eax
440 ; CHECK-NEXT: vpextrb $11, %xmm2, %ecx
441 ; CHECK-NEXT: vpextrb $11, %xmm3, %edx
442 ; CHECK-NEXT: sarb %cl, %dl
443 ; CHECK-NEXT: vpinsrb $10, %eax, %xmm4, %xmm4
444 ; CHECK-NEXT: movzbl %dl, %eax
445 ; CHECK-NEXT: vpinsrb $11, %eax, %xmm4, %xmm4
446 ; CHECK-NEXT: vpextrb $12, %xmm2, %ecx
447 ; CHECK-NEXT: vpextrb $12, %xmm3, %eax
448 ; CHECK-NEXT: sarb %cl, %al
449 ; CHECK-NEXT: movzbl %al, %eax
450 ; CHECK-NEXT: vpinsrb $12, %eax, %xmm4, %xmm4
451 ; CHECK-NEXT: vpextrb $13, %xmm2, %ecx
452 ; CHECK-NEXT: vpextrb $13, %xmm3, %eax
453 ; CHECK-NEXT: sarb %cl, %al
454 ; CHECK-NEXT: vpextrb $14, %xmm2, %ecx
455 ; CHECK-NEXT: vpextrb $14, %xmm3, %edx
456 ; CHECK-NEXT: sarb %cl, %dl
457 ; CHECK-NEXT: movzbl %al, %eax
458 ; CHECK-NEXT: vpinsrb $13, %eax, %xmm4, %xmm4
459 ; CHECK-NEXT: vpextrb $15, %xmm2, %ecx
460 ; CHECK-NEXT: vpextrb $15, %xmm3, %eax
461 ; CHECK-NEXT: sarb %cl, %al
462 ; CHECK-NEXT: vpextrb $1, %xmm1, %ecx
463 ; CHECK-NEXT: vpextrb $1, %xmm0, %esi
464 ; CHECK-NEXT: sarb %cl, %sil
465 ; CHECK-NEXT: movzbl %dl, %ecx
466 ; CHECK-NEXT: vpinsrb $14, %ecx, %xmm4, %xmm2
467 ; CHECK-NEXT: vpextrb $0, %xmm1, %ecx
468 ; CHECK-NEXT: vpextrb $0, %xmm0, %edx
469 ; CHECK-NEXT: sarb %cl, %dl
470 ; CHECK-NEXT: vpextrb $2, %xmm1, %ecx
471 ; CHECK-NEXT: vpextrb $2, %xmm0, %edi
472 ; CHECK-NEXT: sarb %cl, %dil
473 ; CHECK-NEXT: movzbl %al, %eax
474 ; CHECK-NEXT: vpinsrb $15, %eax, %xmm2, %xmm2
475 ; CHECK-NEXT: movzbl %sil, %eax
476 ; CHECK-NEXT: movzbl %dl, %ecx
477 ; CHECK-NEXT: vmovd %ecx, %xmm3
478 ; CHECK-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
479 ; CHECK-NEXT: movzbl %dil, %eax
480 ; CHECK-NEXT: vpextrb $3, %xmm1, %ecx
481 ; CHECK-NEXT: vpextrb $3, %xmm0, %edx
482 ; CHECK-NEXT: sarb %cl, %dl
483 ; CHECK-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
484 ; CHECK-NEXT: movzbl %dl, %eax
485 ; CHECK-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
486 ; CHECK-NEXT: vpextrb $4, %xmm1, %ecx
487 ; CHECK-NEXT: vpextrb $4, %xmm0, %eax
488 ; CHECK-NEXT: sarb %cl, %al
489 ; CHECK-NEXT: movzbl %al, %eax
490 ; CHECK-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
491 ; CHECK-NEXT: vpextrb $5, %xmm1, %ecx
492 ; CHECK-NEXT: vpextrb $5, %xmm0, %eax
493 ; CHECK-NEXT: sarb %cl, %al
494 ; CHECK-NEXT: vpextrb $6, %xmm1, %ecx
495 ; CHECK-NEXT: vpextrb $6, %xmm0, %edx
496 ; CHECK-NEXT: sarb %cl, %dl
497 ; CHECK-NEXT: movzbl %al, %eax
498 ; CHECK-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
499 ; CHECK-NEXT: movzbl %dl, %eax
500 ; CHECK-NEXT: vpextrb $7, %xmm1, %ecx
501 ; CHECK-NEXT: vpextrb $7, %xmm0, %edx
502 ; CHECK-NEXT: sarb %cl, %dl
503 ; CHECK-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
504 ; CHECK-NEXT: movzbl %dl, %eax
505 ; CHECK-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
506 ; CHECK-NEXT: vpextrb $8, %xmm1, %ecx
507 ; CHECK-NEXT: vpextrb $8, %xmm0, %eax
508 ; CHECK-NEXT: sarb %cl, %al
509 ; CHECK-NEXT: movzbl %al, %eax
510 ; CHECK-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
511 ; CHECK-NEXT: vpextrb $9, %xmm1, %ecx
512 ; CHECK-NEXT: vpextrb $9, %xmm0, %eax
513 ; CHECK-NEXT: sarb %cl, %al
514 ; CHECK-NEXT: vpextrb $10, %xmm1, %ecx
515 ; CHECK-NEXT: vpextrb $10, %xmm0, %edx
516 ; CHECK-NEXT: sarb %cl, %dl
517 ; CHECK-NEXT: movzbl %al, %eax
518 ; CHECK-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
519 ; CHECK-NEXT: movzbl %dl, %eax
520 ; CHECK-NEXT: vpextrb $11, %xmm1, %ecx
521 ; CHECK-NEXT: vpextrb $11, %xmm0, %edx
522 ; CHECK-NEXT: sarb %cl, %dl
523 ; CHECK-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
524 ; CHECK-NEXT: movzbl %dl, %eax
525 ; CHECK-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
526 ; CHECK-NEXT: vpextrb $12, %xmm1, %ecx
527 ; CHECK-NEXT: vpextrb $12, %xmm0, %eax
528 ; CHECK-NEXT: sarb %cl, %al
529 ; CHECK-NEXT: movzbl %al, %eax
530 ; CHECK-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
531 ; CHECK-NEXT: vpextrb $13, %xmm1, %ecx
532 ; CHECK-NEXT: vpextrb $13, %xmm0, %eax
533 ; CHECK-NEXT: sarb %cl, %al
534 ; CHECK-NEXT: vpextrb $14, %xmm1, %ecx
535 ; CHECK-NEXT: vpextrb $14, %xmm0, %edx
536 ; CHECK-NEXT: sarb %cl, %dl
537 ; CHECK-NEXT: movzbl %al, %eax
538 ; CHECK-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
539 ; CHECK-NEXT: movzbl %dl, %eax
540 ; CHECK-NEXT: vpextrb $15, %xmm1, %ecx
541 ; CHECK-NEXT: vpextrb $15, %xmm0, %edx
542 ; CHECK-NEXT: sarb %cl, %dl
543 ; CHECK-NEXT: vpinsrb $14, %eax, %xmm3, %xmm0
544 ; CHECK-NEXT: movzbl %dl, %eax
545 ; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
546 ; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
548 %ashr = ashr <32 x i8> %r, %a
552 define <8 x i16> @lshr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {
553 ; CHECK-LABEL: lshr_8i16
554 ; CHECK: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
555 ; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
556 ; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
557 ; CHECK-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero
558 ; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
560 %lshr = lshr <8 x i16> %r, %a
564 define <16 x i16> @lshr_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {
565 ; CHECK-LABEL: lshr_16i16
566 ; CHECK: vpxor %ymm2, %ymm2, %ymm2
567 ; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
568 ; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15]
569 ; CHECK-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3
570 ; CHECK-NEXT: vpsrld $16, %ymm3, %ymm3
571 ; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
572 ; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11]
573 ; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
574 ; CHECK-NEXT: vpsrld $16, %ymm0, %ymm0
575 ; CHECK-NEXT: vpackusdw %ymm3, %ymm0, %ymm0
577 %lshr = lshr <16 x i16> %r, %a
581 define <32 x i8> @lshr_32i8(<32 x i8> %r, <32 x i8> %a) nounwind {
582 ; CHECK-LABEL: lshr_32i8
583 ; CHECK: vextracti128 $1, %ymm1, %xmm2
584 ; CHECK-NEXT: vpextrb $1, %xmm2, %ecx
585 ; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm3
586 ; CHECK-NEXT: vpextrb $1, %xmm3, %eax
587 ; CHECK-NEXT: shrb %cl, %al
588 ; CHECK-NEXT: vpextrb $0, %xmm2, %ecx
589 ; CHECK-NEXT: vpextrb $0, %xmm3, %edx
590 ; CHECK-NEXT: shrb %cl, %dl
591 ; CHECK-NEXT: movzbl %al, %eax
592 ; CHECK-NEXT: movzbl %dl, %edx
593 ; CHECK-NEXT: vpextrb $2, %xmm2, %ecx
594 ; CHECK-NEXT: vpextrb $2, %xmm3, %esi
595 ; CHECK-NEXT: shrb %cl, %sil
596 ; CHECK-NEXT: vmovd %edx, %xmm4
597 ; CHECK-NEXT: vpinsrb $1, %eax, %xmm4, %xmm4
598 ; CHECK-NEXT: movzbl %sil, %eax
599 ; CHECK-NEXT: vpextrb $3, %xmm2, %ecx
600 ; CHECK-NEXT: vpextrb $3, %xmm3, %edx
601 ; CHECK-NEXT: shrb %cl, %dl
602 ; CHECK-NEXT: vpinsrb $2, %eax, %xmm4, %xmm4
603 ; CHECK-NEXT: movzbl %dl, %eax
604 ; CHECK-NEXT: vpinsrb $3, %eax, %xmm4, %xmm4
605 ; CHECK-NEXT: vpextrb $4, %xmm2, %ecx
606 ; CHECK-NEXT: vpextrb $4, %xmm3, %eax
607 ; CHECK-NEXT: shrb %cl, %al
608 ; CHECK-NEXT: movzbl %al, %eax
609 ; CHECK-NEXT: vpinsrb $4, %eax, %xmm4, %xmm4
610 ; CHECK-NEXT: vpextrb $5, %xmm2, %ecx
611 ; CHECK-NEXT: vpextrb $5, %xmm3, %eax
612 ; CHECK-NEXT: shrb %cl, %al
613 ; CHECK-NEXT: vpextrb $6, %xmm2, %ecx
614 ; CHECK-NEXT: vpextrb $6, %xmm3, %edx
615 ; CHECK-NEXT: shrb %cl, %dl
616 ; CHECK-NEXT: movzbl %al, %eax
617 ; CHECK-NEXT: vpinsrb $5, %eax, %xmm4, %xmm4
618 ; CHECK-NEXT: movzbl %dl, %eax
619 ; CHECK-NEXT: vpextrb $7, %xmm2, %ecx
620 ; CHECK-NEXT: vpextrb $7, %xmm3, %edx
621 ; CHECK-NEXT: shrb %cl, %dl
622 ; CHECK-NEXT: vpinsrb $6, %eax, %xmm4, %xmm4
623 ; CHECK-NEXT: movzbl %dl, %eax
624 ; CHECK-NEXT: vpinsrb $7, %eax, %xmm4, %xmm4
625 ; CHECK-NEXT: vpextrb $8, %xmm2, %ecx
626 ; CHECK-NEXT: vpextrb $8, %xmm3, %eax
627 ; CHECK-NEXT: shrb %cl, %al
628 ; CHECK-NEXT: movzbl %al, %eax
629 ; CHECK-NEXT: vpinsrb $8, %eax, %xmm4, %xmm4
630 ; CHECK-NEXT: vpextrb $9, %xmm2, %ecx
631 ; CHECK-NEXT: vpextrb $9, %xmm3, %eax
632 ; CHECK-NEXT: shrb %cl, %al
633 ; CHECK-NEXT: vpextrb $10, %xmm2, %ecx
634 ; CHECK-NEXT: vpextrb $10, %xmm3, %edx
635 ; CHECK-NEXT: shrb %cl, %dl
636 ; CHECK-NEXT: movzbl %al, %eax
637 ; CHECK-NEXT: vpinsrb $9, %eax, %xmm4, %xmm4
638 ; CHECK-NEXT: movzbl %dl, %eax
639 ; CHECK-NEXT: vpextrb $11, %xmm2, %ecx
640 ; CHECK-NEXT: vpextrb $11, %xmm3, %edx
641 ; CHECK-NEXT: shrb %cl, %dl
642 ; CHECK-NEXT: vpinsrb $10, %eax, %xmm4, %xmm4
643 ; CHECK-NEXT: movzbl %dl, %eax
644 ; CHECK-NEXT: vpinsrb $11, %eax, %xmm4, %xmm4
645 ; CHECK-NEXT: vpextrb $12, %xmm2, %ecx
646 ; CHECK-NEXT: vpextrb $12, %xmm3, %eax
647 ; CHECK-NEXT: shrb %cl, %al
648 ; CHECK-NEXT: movzbl %al, %eax
649 ; CHECK-NEXT: vpinsrb $12, %eax, %xmm4, %xmm4
650 ; CHECK-NEXT: vpextrb $13, %xmm2, %ecx
651 ; CHECK-NEXT: vpextrb $13, %xmm3, %eax
652 ; CHECK-NEXT: shrb %cl, %al
653 ; CHECK-NEXT: vpextrb $14, %xmm2, %ecx
654 ; CHECK-NEXT: vpextrb $14, %xmm3, %edx
655 ; CHECK-NEXT: shrb %cl, %dl
656 ; CHECK-NEXT: movzbl %al, %eax
657 ; CHECK-NEXT: vpinsrb $13, %eax, %xmm4, %xmm4
658 ; CHECK-NEXT: vpextrb $15, %xmm2, %ecx
659 ; CHECK-NEXT: vpextrb $15, %xmm3, %eax
660 ; CHECK-NEXT: shrb %cl, %al
661 ; CHECK-NEXT: vpextrb $1, %xmm1, %ecx
662 ; CHECK-NEXT: vpextrb $1, %xmm0, %esi
663 ; CHECK-NEXT: shrb %cl, %sil
664 ; CHECK-NEXT: movzbl %dl, %ecx
665 ; CHECK-NEXT: vpinsrb $14, %ecx, %xmm4, %xmm2
666 ; CHECK-NEXT: vpextrb $0, %xmm1, %ecx
667 ; CHECK-NEXT: vpextrb $0, %xmm0, %edx
668 ; CHECK-NEXT: shrb %cl, %dl
669 ; CHECK-NEXT: vpextrb $2, %xmm1, %ecx
670 ; CHECK-NEXT: vpextrb $2, %xmm0, %edi
671 ; CHECK-NEXT: shrb %cl, %dil
672 ; CHECK-NEXT: movzbl %al, %eax
673 ; CHECK-NEXT: vpinsrb $15, %eax, %xmm2, %xmm2
674 ; CHECK-NEXT: movzbl %sil, %eax
675 ; CHECK-NEXT: movzbl %dl, %ecx
676 ; CHECK-NEXT: vmovd %ecx, %xmm3
677 ; CHECK-NEXT: vpinsrb $1, %eax, %xmm3, %xmm3
678 ; CHECK-NEXT: movzbl %dil, %eax
679 ; CHECK-NEXT: vpextrb $3, %xmm1, %ecx
680 ; CHECK-NEXT: vpextrb $3, %xmm0, %edx
681 ; CHECK-NEXT: shrb %cl, %dl
682 ; CHECK-NEXT: vpinsrb $2, %eax, %xmm3, %xmm3
683 ; CHECK-NEXT: movzbl %dl, %eax
684 ; CHECK-NEXT: vpinsrb $3, %eax, %xmm3, %xmm3
685 ; CHECK-NEXT: vpextrb $4, %xmm1, %ecx
686 ; CHECK-NEXT: vpextrb $4, %xmm0, %eax
687 ; CHECK-NEXT: shrb %cl, %al
688 ; CHECK-NEXT: movzbl %al, %eax
689 ; CHECK-NEXT: vpinsrb $4, %eax, %xmm3, %xmm3
690 ; CHECK-NEXT: vpextrb $5, %xmm1, %ecx
691 ; CHECK-NEXT: vpextrb $5, %xmm0, %eax
692 ; CHECK-NEXT: shrb %cl, %al
693 ; CHECK-NEXT: vpextrb $6, %xmm1, %ecx
694 ; CHECK-NEXT: vpextrb $6, %xmm0, %edx
695 ; CHECK-NEXT: shrb %cl, %dl
696 ; CHECK-NEXT: movzbl %al, %eax
697 ; CHECK-NEXT: vpinsrb $5, %eax, %xmm3, %xmm3
698 ; CHECK-NEXT: movzbl %dl, %eax
699 ; CHECK-NEXT: vpextrb $7, %xmm1, %ecx
700 ; CHECK-NEXT: vpextrb $7, %xmm0, %edx
701 ; CHECK-NEXT: shrb %cl, %dl
702 ; CHECK-NEXT: vpinsrb $6, %eax, %xmm3, %xmm3
703 ; CHECK-NEXT: movzbl %dl, %eax
704 ; CHECK-NEXT: vpinsrb $7, %eax, %xmm3, %xmm3
705 ; CHECK-NEXT: vpextrb $8, %xmm1, %ecx
706 ; CHECK-NEXT: vpextrb $8, %xmm0, %eax
707 ; CHECK-NEXT: shrb %cl, %al
708 ; CHECK-NEXT: movzbl %al, %eax
709 ; CHECK-NEXT: vpinsrb $8, %eax, %xmm3, %xmm3
710 ; CHECK-NEXT: vpextrb $9, %xmm1, %ecx
711 ; CHECK-NEXT: vpextrb $9, %xmm0, %eax
712 ; CHECK-NEXT: shrb %cl, %al
713 ; CHECK-NEXT: vpextrb $10, %xmm1, %ecx
714 ; CHECK-NEXT: vpextrb $10, %xmm0, %edx
715 ; CHECK-NEXT: shrb %cl, %dl
716 ; CHECK-NEXT: movzbl %al, %eax
717 ; CHECK-NEXT: vpinsrb $9, %eax, %xmm3, %xmm3
718 ; CHECK-NEXT: movzbl %dl, %eax
719 ; CHECK-NEXT: vpextrb $11, %xmm1, %ecx
720 ; CHECK-NEXT: vpextrb $11, %xmm0, %edx
721 ; CHECK-NEXT: shrb %cl, %dl
722 ; CHECK-NEXT: vpinsrb $10, %eax, %xmm3, %xmm3
723 ; CHECK-NEXT: movzbl %dl, %eax
724 ; CHECK-NEXT: vpinsrb $11, %eax, %xmm3, %xmm3
725 ; CHECK-NEXT: vpextrb $12, %xmm1, %ecx
726 ; CHECK-NEXT: vpextrb $12, %xmm0, %eax
727 ; CHECK-NEXT: shrb %cl, %al
728 ; CHECK-NEXT: movzbl %al, %eax
729 ; CHECK-NEXT: vpinsrb $12, %eax, %xmm3, %xmm3
730 ; CHECK-NEXT: vpextrb $13, %xmm1, %ecx
731 ; CHECK-NEXT: vpextrb $13, %xmm0, %eax
732 ; CHECK-NEXT: shrb %cl, %al
733 ; CHECK-NEXT: vpextrb $14, %xmm1, %ecx
734 ; CHECK-NEXT: vpextrb $14, %xmm0, %edx
735 ; CHECK-NEXT: shrb %cl, %dl
736 ; CHECK-NEXT: movzbl %al, %eax
737 ; CHECK-NEXT: vpinsrb $13, %eax, %xmm3, %xmm3
738 ; CHECK-NEXT: movzbl %dl, %eax
739 ; CHECK-NEXT: vpextrb $15, %xmm1, %ecx
740 ; CHECK-NEXT: vpextrb $15, %xmm0, %edx
741 ; CHECK-NEXT: shrb %cl, %dl
742 ; CHECK-NEXT: vpinsrb $14, %eax, %xmm3, %xmm0
743 ; CHECK-NEXT: movzbl %dl, %eax
744 ; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
745 ; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
747 %lshr = lshr <32 x i8> %r, %a