1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd -mattr=+avx512vl| FileCheck %s
3 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readonly
5 declare <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32>, <4 x i32>, i8)
7 define <4 x i32>@test_int_x86_avx512_mask_vplzcnt_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) {
8 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_d_128:
10 ; CHECK-NEXT: movzbl %dil, %eax
11 ; CHECK-NEXT: kmovw %eax, %k1
12 ; CHECK-NEXT: vplzcntd %xmm0, %xmm1 {%k1}
13 ; CHECK-NEXT: vplzcntd %xmm0, %xmm2 {%k1} {z}
14 ; CHECK-NEXT: vplzcntd %xmm0, %xmm0
15 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
16 ; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
18 %res = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2)
19 %res1 = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1)
20 %res3 = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> zeroinitializer, i8 %x2)
21 %res2 = add <4 x i32> %res, %res1
22 %res4 = add <4 x i32> %res2, %res3
26 declare <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32>, <8 x i32>, i8)
28 define <8 x i32>@test_int_x86_avx512_mask_vplzcnt_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) {
29 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_d_256:
31 ; CHECK-NEXT: movzbl %dil, %eax
32 ; CHECK-NEXT: kmovw %eax, %k1
33 ; CHECK-NEXT: vplzcntd %ymm0, %ymm1 {%k1}
34 ; CHECK-NEXT: vplzcntd %ymm0, %ymm0
35 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
37 %res = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2)
38 %res1 = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 -1)
39 %res2 = add <8 x i32> %res, %res1
43 declare <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64>, <2 x i64>, i8)
45 define <2 x i64>@test_int_x86_avx512_mask_vplzcnt_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) {
46 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_q_128:
48 ; CHECK-NEXT: movzbl %dil, %eax
49 ; CHECK-NEXT: kmovw %eax, %k1
50 ; CHECK-NEXT: vplzcntq %xmm0, %xmm1 {%k1}
51 ; CHECK-NEXT: vplzcntq %xmm0, %xmm0
52 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
54 %res = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2)
55 %res1 = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 -1)
56 %res2 = add <2 x i64> %res, %res1
60 declare <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64>, <4 x i64>, i8)
62 define <4 x i64>@test_int_x86_avx512_mask_vplzcnt_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) {
63 ; CHECK-LABEL: test_int_x86_avx512_mask_vplzcnt_q_256:
65 ; CHECK-NEXT: movzbl %dil, %eax
66 ; CHECK-NEXT: kmovw %eax, %k1
67 ; CHECK-NEXT: vplzcntq %ymm0, %ymm1 {%k1}
68 ; CHECK-NEXT: vplzcntq %ymm0, %ymm0
69 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
71 %res = call <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2)
72 %res1 = call <4 x i64> @llvm.x86.avx512.mask.lzcnt.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 -1)
73 %res2 = add <4 x i64> %res, %res1
77 declare <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32>, <4 x i32>, i8)
79 define <4 x i32>@test_int_x86_avx512_mask_vpconflict_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) {
80 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_d_128:
82 ; CHECK-NEXT: movzbl %dil, %eax
83 ; CHECK-NEXT: kmovw %eax, %k1
84 ; CHECK-NEXT: vpconflictd %xmm0, %xmm1 {%k1}
85 ; CHECK-NEXT: vpconflictd %xmm0, %xmm2 {%k1} {z}
86 ; CHECK-NEXT: vpconflictd %xmm0, %xmm0
87 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
88 ; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
90 %res = call <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2)
91 %res1 = call <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1)
92 %res3 = call <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32> %x0, <4 x i32> zeroinitializer, i8 %x2)
93 %res2 = add <4 x i32> %res, %res1
94 %res4 = add <4 x i32> %res2, %res3
98 declare <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32>, <8 x i32>, i8)
100 define <8 x i32>@test_int_x86_avx512_mask_vpconflict_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) {
101 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_d_256:
103 ; CHECK-NEXT: movzbl %dil, %eax
104 ; CHECK-NEXT: kmovw %eax, %k1
105 ; CHECK-NEXT: vpconflictd %ymm0, %ymm1 {%k1}
106 ; CHECK-NEXT: vpconflictd %ymm0, %ymm0
107 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
109 %res = call <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2)
110 %res1 = call <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 -1)
111 %res2 = add <8 x i32> %res, %res1
115 declare <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64>, <2 x i64>, i8)
117 define <2 x i64>@test_int_x86_avx512_mask_vpconflict_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) {
118 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_q_128:
120 ; CHECK-NEXT: movzbl %dil, %eax
121 ; CHECK-NEXT: kmovw %eax, %k1
122 ; CHECK-NEXT: vpconflictq %xmm0, %xmm1 {%k1}
123 ; CHECK-NEXT: vpconflictq %xmm0, %xmm0
124 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
126 %res = call <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2)
127 %res1 = call <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 -1)
128 %res2 = add <2 x i64> %res, %res1
132 declare <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64>, <4 x i64>, i8)
134 define <4 x i64>@test_int_x86_avx512_mask_vpconflict_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) {
135 ; CHECK-LABEL: test_int_x86_avx512_mask_vpconflict_q_256:
137 ; CHECK-NEXT: movzbl %dil, %eax
138 ; CHECK-NEXT: kmovw %eax, %k1
139 ; CHECK-NEXT: vpconflictq %ymm0, %ymm1 {%k1}
140 ; CHECK-NEXT: vpconflictq %ymm0, %ymm0
141 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
143 %res = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2)
144 %res1 = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 -1)
145 %res2 = add <4 x i64> %res, %res1
149 define <8 x i32> @test_x86_vbroadcastmw_256(i16 %a0) {
150 ; CHECK: test_x86_vbroadcastmw_256
151 ; CHECK: vpbroadcastmw2d %k0, %ymm0
152 %res = call <8 x i32> @llvm.x86.avx512.broadcastmw.256(i16 %a0) ;
155 declare <8 x i32> @llvm.x86.avx512.broadcastmw.256(i16)
157 define <4 x i32> @test_x86_vbroadcastmw_128(i16 %a0) {
158 ; CHECK: test_x86_vbroadcastmw_128
159 ; CHECK: vpbroadcastmw2d %k0, %xmm0
160 %res = call <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16 %a0) ;
163 declare <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16)
165 define <4 x i64> @test_x86_broadcastmb_256(i8 %a0) {
166 ; CHECK: test_x86_broadcastmb_256
167 ; CHECK: vpbroadcastmb2q %k0, %ymm0
168 %res = call <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8 %a0) ;
171 declare <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8)
173 define <2 x i64> @test_x86_broadcastmb_128(i8 %a0) {
174 ; CHECK: test_x86_broadcastmb_128
175 ; CHECK: vpbroadcastmb2q %k0, %xmm0
176 %res = call <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8 %a0) ;
179 declare <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8)