1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s
4 ; In this test we check that sign-extend of the mask bit is performed by
5 ; shifting the needed bit to the MSB, and not using shl+sra.
7 ;CHECK-LABEL: vsel_float:
8 ;CHECK: movl $-2147483648
12 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
13 %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
17 ;CHECK-LABEL: vsel_4xi8:
18 ;CHECK: movl $-2147483648
22 define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
23 %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i8> %v1, <4 x i8> %v2
28 ; We do not have native support for v8i16 blends and we have to use the
29 ; blendvb instruction or a sequence of NAND/OR/AND. Make sure that we do not r
30 ; reduce the mask in this case.
31 ;CHECK-LABEL: vsel_8xi16:
36 define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {
37 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i16> %v1, <8 x i16> %v2