1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
3 declare i8 @llvm.cttz.i8(i8, i1)
4 declare i16 @llvm.cttz.i16(i16, i1)
5 declare i32 @llvm.cttz.i32(i32, i1)
6 declare i64 @llvm.cttz.i64(i64, i1)
7 declare i8 @llvm.ctlz.i8(i8, i1)
8 declare i16 @llvm.ctlz.i16(i16, i1)
9 declare i32 @llvm.ctlz.i32(i32, i1)
10 declare i64 @llvm.ctlz.i64(i64, i1)
12 define i8 @cttz_i8(i8 %x) {
13 ; CHECK-LABEL: cttz_i8:
15 ; CHECK-NEXT: movzbl %dil, %eax
16 ; CHECK-NEXT: bsfl %eax, %eax
18 %tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true )
22 define i16 @cttz_i16(i16 %x) {
23 ; CHECK-LABEL: cttz_i16:
25 ; CHECK-NEXT: bsfw %di, %ax
27 %tmp = call i16 @llvm.cttz.i16( i16 %x, i1 true )
31 define i32 @cttz_i32(i32 %x) {
32 ; CHECK-LABEL: cttz_i32:
34 ; CHECK-NEXT: bsfl %edi, %eax
36 %tmp = call i32 @llvm.cttz.i32( i32 %x, i1 true )
40 define i64 @cttz_i64(i64 %x) {
41 ; CHECK-LABEL: cttz_i64:
43 ; CHECK-NEXT: bsfq %rdi, %rax
45 %tmp = call i64 @llvm.cttz.i64( i64 %x, i1 true )
49 define i8 @ctlz_i8(i8 %x) {
50 ; CHECK-LABEL: ctlz_i8:
52 ; CHECK-NEXT: movzbl %dil, %eax
53 ; CHECK-NEXT: bsrl %eax, %eax
54 ; CHECK-NEXT: xorl $7, %eax
56 %tmp2 = call i8 @llvm.ctlz.i8( i8 %x, i1 true )
60 define i16 @ctlz_i16(i16 %x) {
61 ; CHECK-LABEL: ctlz_i16:
63 ; CHECK-NEXT: bsrw %di, %ax
64 ; CHECK-NEXT: xorl $15, %eax
66 %tmp2 = call i16 @llvm.ctlz.i16( i16 %x, i1 true )
70 define i32 @ctlz_i32(i32 %x) {
71 ; CHECK-LABEL: ctlz_i32:
73 ; CHECK-NEXT: bsrl %edi, %eax
74 ; CHECK-NEXT: xorl $31, %eax
76 %tmp = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
80 define i64 @ctlz_i64(i64 %x) {
81 ; CHECK-LABEL: ctlz_i64:
83 ; CHECK-NEXT: bsrq %rdi, %rax
84 ; CHECK-NEXT: xorq $63, %rax
86 %tmp = call i64 @llvm.ctlz.i64( i64 %x, i1 true )
90 define i32 @ctlz_i32_zero_test(i32 %n) {
91 ; Generate a test and branch to handle zero inputs because bsr/bsf are very slow.
93 ; CHECK-LABEL: ctlz_i32_zero_test:
95 ; CHECK-NEXT: movl $32, %eax
96 ; CHECK-NEXT: testl %edi, %edi
97 ; CHECK-NEXT: je .LBB8_2
98 ; CHECK-NEXT: # BB#1: # %cond.false
99 ; CHECK-NEXT: bsrl %edi, %eax
100 ; CHECK-NEXT: xorl $31, %eax
101 ; CHECK-NEXT: .LBB8_2: # %cond.end
103 %tmp1 = call i32 @llvm.ctlz.i32(i32 %n, i1 false)
107 define i32 @ctlz_i32_fold_cmov(i32 %n) {
108 ; Don't generate the cmovne when the source is known non-zero (and bsr would
111 ; FIXME: The compare and branch are produced late in IR (by CodeGenPrepare), and
112 ; codegen doesn't know how to delete the movl and je.
114 ; CHECK-LABEL: ctlz_i32_fold_cmov:
116 ; CHECK-NEXT: orl $1, %edi
117 ; CHECK-NEXT: movl $32, %eax
118 ; CHECK-NEXT: je .LBB9_2
119 ; CHECK-NEXT: # BB#1: # %cond.false
120 ; CHECK-NEXT: bsrl %edi, %eax
121 ; CHECK-NEXT: xorl $31, %eax
122 ; CHECK-NEXT: .LBB9_2: # %cond.end
125 %tmp1 = call i32 @llvm.ctlz.i32(i32 %or, i1 false)
129 define i32 @ctlz_bsr(i32 %n) {
130 ; Don't generate any xors when a 'ctlz' intrinsic is actually used to compute
131 ; the most significant bit, which is what 'bsr' does natively.
133 ; CHECK-LABEL: ctlz_bsr:
135 ; CHECK-NEXT: bsrl %edi, %eax
137 %ctlz = call i32 @llvm.ctlz.i32(i32 %n, i1 true)
138 %bsr = xor i32 %ctlz, 31
142 define i32 @ctlz_bsr_zero_test(i32 %n) {
143 ; Generate a test and branch to handle zero inputs because bsr/bsf are very slow.
144 ; FIXME: The compare and branch are produced late in IR (by CodeGenPrepare), and
145 ; codegen doesn't know how to combine the $32 and $31 into $63.
147 ; CHECK-LABEL: ctlz_bsr_zero_test:
149 ; CHECK-NEXT: movl $32, %eax
150 ; CHECK-NEXT: testl %edi, %edi
151 ; CHECK-NEXT: je .LBB11_2
152 ; CHECK-NEXT: # BB#1: # %cond.false
153 ; CHECK-NEXT: bsrl %edi, %eax
154 ; CHECK-NEXT: xorl $31, %eax
155 ; CHECK-NEXT: .LBB11_2: # %cond.end
156 ; CHECK-NEXT: xorl $31, %eax
158 %ctlz = call i32 @llvm.ctlz.i32(i32 %n, i1 false)
159 %bsr = xor i32 %ctlz, 31