1 ; RUN: opt -S -codegenprepare %s -o - | FileCheck %s
2 ; RUN: opt -S -codegenprepare -addr-sink-using-gep=1 %s -o - | FileCheck -check-prefix=CHECK-GEP %s
3 ; This file tests the different cases what are involved when codegen prepare
4 ; tries to get sign extension out of the way of addressing mode.
5 ; This tests require an actual target as addressing mode decisions depends
8 target datalayout = "e-i64:64-f80:128-s:64-n8:16:32:64-S128"
9 target triple = "x86_64-apple-macosx"
12 ; Check that we correctly promote both operands of the promotable add.
13 ; CHECK-LABEL: @twoArgsPromotion
14 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64
15 ; CHECK: [[ARG2SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg2 to i64
16 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], [[ARG2SEXT]]
17 ; CHECK: inttoptr i64 [[PROMOTED]] to i8*
19 define i8 @twoArgsPromotion(i32 %arg1, i32 %arg2) {
20 %add = add nsw i32 %arg1, %arg2
21 %sextadd = sext i32 %add to i64
22 %base = inttoptr i64 %sextadd to i8*
27 ; Check that we do not promote both operands of the promotable add when
28 ; the instruction will not be folded into the addressing mode.
29 ; Otherwise, we will increase the number of instruction executed.
30 ; (This is a heuristic of course, because the new sext could have been
31 ; merged with something else.)
32 ; CHECK-LABEL: @twoArgsNoPromotion
33 ; CHECK: add nsw i32 %arg1, %arg2
35 define i8 @twoArgsNoPromotion(i32 %arg1, i32 %arg2, i8* %base) {
36 %add = add nsw i32 %arg1, %arg2
37 %sextadd = sext i32 %add to i64
38 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
39 %res = load i8* %arrayidx
43 ; Check that we do not promote when the related instruction does not have
45 ; CHECK-LABEL: @noPromotion
48 define i8 @noPromotion(i32 %arg1, i32 %arg2, i8* %base) {
49 %add = add i32 %arg1, %arg2
50 %sextadd = sext i32 %add to i64
51 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
52 %res = load i8* %arrayidx
56 ; Check that we correctly promote constant arguments.
57 ; CHECK-LABEL: @oneArgPromotion
58 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64
59 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
60 ; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
62 define i8 @oneArgPromotion(i32 %arg1, i8* %base) {
63 %add = add nsw i32 %arg1, 1
64 %sextadd = sext i32 %add to i64
65 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
66 %res = load i8* %arrayidx
70 ; Check that we are able to merge a sign extension with a zero extension.
71 ; CHECK-LABEL: @oneArgPromotionZExt
72 ; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64
73 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1ZEXT]], 1
74 ; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
76 define i8 @oneArgPromotionZExt(i8 %arg1, i8* %base) {
77 %zext = zext i8 %arg1 to i32
78 %add = add nsw i32 %zext, 1
79 %sextadd = sext i32 %add to i64
80 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
81 %res = load i8* %arrayidx
85 ; Check that we do not promote truncate when we cannot determine the
86 ; bits that are dropped.
87 ; CHECK-LABEL: @oneArgPromotionBlockTrunc1
88 ; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 %arg1 to i8
89 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64
90 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
91 ; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
93 define i8 @oneArgPromotionBlockTrunc1(i32 %arg1, i8* %base) {
94 %trunc = trunc i32 %arg1 to i8
95 %add = add nsw i8 %trunc, 1
96 %sextadd = sext i8 %add to i64
97 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
98 %res = load i8* %arrayidx
102 ; Check that we do not promote truncate when we cannot determine all the
103 ; bits that are dropped.
104 ; CHECK-LABEL: @oneArgPromotionBlockTrunc2
105 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i16 %arg1 to i32
106 ; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[ARG1SEXT]] to i8
107 ; CHECK: [[ARG1SEXT64:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64
108 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT64]], 1
109 ; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
111 define i8 @oneArgPromotionBlockTrunc2(i16 %arg1, i8* %base) {
112 %sextarg1 = sext i16 %arg1 to i32
113 %trunc = trunc i32 %sextarg1 to i8
114 %add = add nsw i8 %trunc, 1
115 %sextadd = sext i8 %add to i64
116 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
117 %res = load i8* %arrayidx
121 ; Check that we are able to promote truncate when we know all the bits
123 ; CHECK-LABEL: @oneArgPromotionPassTruncKeepSExt
124 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i64
125 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
126 ; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
128 define i8 @oneArgPromotionPassTruncKeepSExt(i1 %arg1, i8* %base) {
129 %sextarg1 = sext i1 %arg1 to i32
130 %trunc = trunc i32 %sextarg1 to i8
131 %add = add nsw i8 %trunc, 1
132 %sextadd = sext i8 %add to i64
133 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
134 %res = load i8* %arrayidx
138 ; On X86 truncate are free. Check that we are able to promote the add
139 ; to be used as addressing mode and that we insert a truncate for the other
141 ; CHECK-LABEL: @oneArgPromotionTruncInsert
142 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64
143 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
144 ; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i64 [[PROMOTED]] to i8
145 ; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8* %base, i64 [[PROMOTED]]
146 ; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8* [[GEP]]
147 ; CHECK: add i8 [[LOAD]], [[TRUNC]]
149 define i8 @oneArgPromotionTruncInsert(i8 %arg1, i8* %base) {
150 %add = add nsw i8 %arg1, 1
151 %sextadd = sext i8 %add to i64
152 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
153 %res = load i8* %arrayidx
154 %finalres = add i8 %res, %add
158 ; Cannot sext from a larger type than the promoted type.
159 ; CHECK-LABEL: @oneArgPromotionLargerType
160 ; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i128 %arg1 to i8
161 ; CHECK: [[ARG1SEXT64:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64
162 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT64]], 1
163 ; CHECK: getelementptr inbounds i8* %base, i64 [[PROMOTED]]
165 define i8 @oneArgPromotionLargerType(i128 %arg1, i8* %base) {
166 %trunc = trunc i128 %arg1 to i8
167 %add = add nsw i8 %trunc, 1
168 %sextadd = sext i8 %add to i64
169 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
170 %res = load i8* %arrayidx
171 %finalres = add i8 %res, %add
175 ; Use same inserted trunc
176 ; On X86 truncate are free. Check that we are able to promote the add
177 ; to be used as addressing mode and that we insert a truncate for
178 ; *all* the other uses.
179 ; CHECK-LABEL: @oneArgPromotionTruncInsertSeveralUse
180 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64
181 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
182 ; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i64 [[PROMOTED]] to i8
183 ; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8* %base, i64 [[PROMOTED]]
184 ; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8* [[GEP]]
185 ; CHECK: [[ADDRES:%[a-zA-Z_0-9-]+]] = add i8 [[LOAD]], [[TRUNC]]
186 ; CHECK: add i8 [[ADDRES]], [[TRUNC]]
188 define i8 @oneArgPromotionTruncInsertSeveralUse(i8 %arg1, i8* %base) {
189 %add = add nsw i8 %arg1, 1
190 %sextadd = sext i8 %add to i64
191 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
192 %res = load i8* %arrayidx
193 %almostfinalres = add i8 %res, %add
194 %finalres = add i8 %almostfinalres, %add
198 ; Check that the promoted instruction is used for all uses of the original
200 ; CHECK-LABEL: @oneArgPromotionSExtSeveralUse
201 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64
202 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1
203 ; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8* %base, i64 [[PROMOTED]]
204 ; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8* [[GEP]]
205 ; CHECK: [[ADDRES:%[a-zA-Z_0-9-]+]] = zext i8 [[LOAD]] to i64
206 ; CHECK: add i64 [[ADDRES]], [[PROMOTED]]
208 define i64 @oneArgPromotionSExtSeveralUse(i8 %arg1, i8* %base) {
209 %add = add nsw i8 %arg1, 1
210 %sextadd = sext i8 %add to i64
211 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
212 %res = load i8* %arrayidx
213 %almostfinalres = zext i8 %res to i64
214 %finalres = add i64 %almostfinalres, %sextadd
218 ; Check all types of rollback mechanism.
219 ; For this test, the sign extension stays in place.
220 ; However, the matching process goes until promoting both the operands
221 ; of the first promotable add implies.
222 ; At this point the rollback mechanism kicks in and restores the states
223 ; until the addressing mode matcher is able to match something: in that
224 ; case promote nothing.
225 ; Along the way, the promotion mechanism involves:
226 ; - Mutating the type of %promotableadd1 and %promotableadd2.
227 ; - Creating a sext for %arg1 and %arg2.
228 ; - Creating a trunc for a use of %promotableadd1.
229 ; - Replacing a bunch of uses.
230 ; - Setting the operands of the promoted instruction with the promoted values.
231 ; - Moving instruction around (mainly sext when promoting instruction).
232 ; Each type of those promotions has to be undo at least once during this
234 ; CHECK-LABEL: @twoArgsPromotionNest
235 ; CHECK: [[ORIG:%[a-zA-Z_0-9-]+]] = add nsw i32 %arg1, %arg2
236 ; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ORIG]], [[ORIG]]
237 ; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
238 ; CHECK: getelementptr inbounds i8* %base, i64 [[SEXT]]
240 define i8 @twoArgsPromotionNest(i32 %arg1, i32 %arg2, i8* %base) {
241 %promotableadd1 = add nsw i32 %arg1, %arg2
242 %promotableadd2 = add nsw i32 %promotableadd1, %promotableadd1
243 %sextadd = sext i32 %promotableadd2 to i64
244 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
245 %res = load i8* %arrayidx
249 ; Test the InstructionRemover undo, which was the only one not
250 ; kicked in the previous test.
251 ; The matcher first promotes the add, removes the trunc and promotes
253 ; Then, the matcher cannot use an addressing mode r + r + r, thus it
255 ; CHECK-LABEL: @twoArgsNoPromotionRemove
256 ; CHECK: [[SEXTARG1:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i32
257 ; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[SEXTARG1]] to i8
258 ; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[TRUNC]], %arg2
259 ; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i64
260 ; CHECK: getelementptr inbounds i8* %base, i64 [[SEXT]]
262 define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, i8* %base) {
263 %sextarg1 = sext i1 %arg1 to i32
264 %trunc = trunc i32 %sextarg1 to i8
265 %add = add nsw i8 %trunc, %arg2
266 %sextadd = sext i8 %add to i64
267 %arrayidx = getelementptr inbounds i8* %base, i64 %sextadd
268 %res = load i8* %arrayidx
272 ; Ensure that when the profitability checks kicks in, the IR is not modified
273 ; will IgnoreProfitability is on.
274 ; The profitabily check happens when a candidate instruction has several uses.
275 ; The matcher will create a new matcher for each use and check if the
276 ; instruction is in the list of the matched instructions of this new matcher.
277 ; All changes made by the new matchers must be dropped before pursuing
278 ; otherwise the state of the original matcher will be wrong.
280 ; Without the profitability check, when checking for the second use of
281 ; arrayidx, the matcher promotes everything all the way to %arg1, %arg2.
282 ; Check that we did not promote anything in the final matching.
284 ; <rdar://problem/16020230>
285 ; CHECK-LABEL: @checkProfitability
286 ; CHECK-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg1 to i64
287 ; CHECK-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg2 to i64
288 ; CHECK: [[SHL:%[a-zA-Z_0-9-]+]] = shl nsw i32 %arg1, 1
289 ; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SHL]], %arg2
290 ; CHECK: [[SEXTADD:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
292 ; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48
293 ; CHECK: [[ADDR1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE1]] to i32*
294 ; CHECK: load i32* [[ADDR1]]
296 ; CHECK: [[BASE2:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48
297 ; CHECK: [[ADDR2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE2]] to i32*
298 ; CHECK: load i32* [[ADDR2]]
300 ; CHECK-GEP-LABEL: @checkProfitability
301 ; CHECK-GEP-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg1 to i64
302 ; CHECK-GEP-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg2 to i64
303 ; CHECK-GEP: [[SHL:%[a-zA-Z_0-9-]+]] = shl nsw i32 %arg1, 1
304 ; CHECK-GEP: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SHL]], %arg2
305 ; CHECK-GEP: [[SEXTADD:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
307 ; CHECK-GEP: [[BASE1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to i32*
308 ; CHECK-GEP: [[BCC1:%[a-zA-Z_0-9-]+]] = bitcast i32* [[BASE1]] to i8*
309 ; CHECK-GEP: [[FULL1:%[a-zA-Z_0-9-]+]] = getelementptr i8* [[BCC1]], i64 48
310 ; CHECK-GEP: [[ADDR1:%[a-zA-Z_0-9-]+]] = bitcast i8* [[FULL1]] to i32*
311 ; CHECK-GEP: load i32* [[ADDR1]]
313 ; CHECK-GEP: [[BASE2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to i32*
314 ; CHECK-GEP: [[BCC2:%[a-zA-Z_0-9-]+]] = bitcast i32* [[BASE2]] to i8*
315 ; CHECK-GEP: [[FULL2:%[a-zA-Z_0-9-]+]] = getelementptr i8* [[BCC2]], i64 48
316 ; CHECK-GEP: [[ADDR2:%[a-zA-Z_0-9-]+]] = bitcast i8* [[FULL2]] to i32*
317 ; CHECK-GEP: load i32* [[ADDR2]]
319 define i32 @checkProfitability(i32 %arg1, i32 %arg2, i1 %test) {
320 %shl = shl nsw i32 %arg1, 1
321 %add1 = add nsw i32 %shl, %arg2
322 %sextidx1 = sext i32 %add1 to i64
323 %tmpptr = inttoptr i64 %sextidx1 to i32*
324 %arrayidx1 = getelementptr i32* %tmpptr, i64 12
325 br i1 %test, label %then, label %else
327 %res1 = load i32* %arrayidx1
330 %res2 = load i32* %arrayidx1
333 %tmp = phi i32 [%res1, %then], [%res2, %else]
334 %res = add i32 %tmp, %add1
335 %addr = inttoptr i32 %res to i32*
336 %final = load i32* %addr