1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
4 ; Verify that each of the following test cases is folded into a single
5 ; instruction which performs a blend operation.
7 define <2 x i64> @test1(<2 x i64> %a, <2 x i64> %b) {
10 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
12 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
13 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1>
14 %or = or <2 x i64> %shuf1, %shuf2
19 define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) {
22 ; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]
23 ; CHECK-NEXT: movdqa %xmm1, %xmm0
25 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
26 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
27 %or = or <4 x i32> %shuf1, %shuf2
32 define <2 x i64> @test3(<2 x i64> %a, <2 x i64> %b) {
35 ; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]
36 ; CHECK-NEXT: movdqa %xmm1, %xmm0
38 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1>
39 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
40 %or = or <2 x i64> %shuf1, %shuf2
45 define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b) {
48 ; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
49 ; CHECK-NEXT: movdqa %xmm1, %xmm0
51 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
52 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3>
53 %or = or <4 x i32> %shuf1, %shuf2
58 define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
61 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
63 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3>
64 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
65 %or = or <4 x i32> %shuf1, %shuf2
70 define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b) {
73 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
75 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
76 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
77 %or = or <4 x i32> %shuf1, %shuf2
82 define <4 x i32> @test7(<4 x i32> %a, <4 x i32> %b) {
85 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
87 %and1 = and <4 x i32> %a, <i32 -1, i32 -1, i32 0, i32 0>
88 %and2 = and <4 x i32> %b, <i32 0, i32 0, i32 -1, i32 -1>
89 %or = or <4 x i32> %and1, %and2
94 define <2 x i64> @test8(<2 x i64> %a, <2 x i64> %b) {
97 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
99 %and1 = and <2 x i64> %a, <i64 -1, i64 0>
100 %and2 = and <2 x i64> %b, <i64 0, i64 -1>
101 %or = or <2 x i64> %and1, %and2
106 define <4 x i32> @test9(<4 x i32> %a, <4 x i32> %b) {
107 ; CHECK-LABEL: test9:
109 ; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]
110 ; CHECK-NEXT: movdqa %xmm1, %xmm0
112 %and1 = and <4 x i32> %a, <i32 0, i32 0, i32 -1, i32 -1>
113 %and2 = and <4 x i32> %b, <i32 -1, i32 -1, i32 0, i32 0>
114 %or = or <4 x i32> %and1, %and2
119 define <2 x i64> @test10(<2 x i64> %a, <2 x i64> %b) {
120 ; CHECK-LABEL: test10:
122 ; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]
123 ; CHECK-NEXT: movdqa %xmm1, %xmm0
125 %and1 = and <2 x i64> %a, <i64 0, i64 -1>
126 %and2 = and <2 x i64> %b, <i64 -1, i64 0>
127 %or = or <2 x i64> %and1, %and2
132 define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
133 ; CHECK-LABEL: test11:
135 ; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
136 ; CHECK-NEXT: movdqa %xmm1, %xmm0
138 %and1 = and <4 x i32> %a, <i32 -1, i32 0, i32 0, i32 0>
139 %and2 = and <4 x i32> %b, <i32 0, i32 -1, i32 -1, i32 -1>
140 %or = or <4 x i32> %and1, %and2
145 define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) {
146 ; CHECK-LABEL: test12:
148 ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
150 %and1 = and <4 x i32> %a, <i32 0, i32 -1, i32 -1, i32 -1>
151 %and2 = and <4 x i32> %b, <i32 -1, i32 0, i32 0, i32 0>
152 %or = or <4 x i32> %and1, %and2
157 ; Verify that the following test cases are folded into single shuffles.
159 define <4 x i32> @test13(<4 x i32> %a, <4 x i32> %b) {
160 ; CHECK-LABEL: test13:
162 ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3]
164 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 1, i32 1, i32 4, i32 4>
165 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
166 %or = or <4 x i32> %shuf1, %shuf2
171 define <2 x i64> @test14(<2 x i64> %a, <2 x i64> %b) {
172 ; CHECK-LABEL: test14:
174 ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
176 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
177 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
178 %or = or <2 x i64> %shuf1, %shuf2
183 define <4 x i32> @test15(<4 x i32> %a, <4 x i32> %b) {
184 ; CHECK-LABEL: test15:
186 ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,1],xmm0[2,1]
187 ; CHECK-NEXT: movaps %xmm1, %xmm0
189 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 1>
190 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 2, i32 1, i32 4, i32 4>
191 %or = or <4 x i32> %shuf1, %shuf2
196 define <2 x i64> @test16(<2 x i64> %a, <2 x i64> %b) {
197 ; CHECK-LABEL: test16:
199 ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
200 ; CHECK-NEXT: movdqa %xmm1, %xmm0
202 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
203 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
204 %or = or <2 x i64> %shuf1, %shuf2
209 ; Verify that the dag-combiner does not fold a OR of two shuffles into a single
210 ; shuffle instruction when the shuffle indexes are not compatible.
212 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
213 ; CHECK-LABEL: test17:
215 ; CHECK-NEXT: xorps %xmm2, %xmm2
216 ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,0]
217 ; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[0,2]
218 ; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
219 ; CHECK-NEXT: orps %xmm1, %xmm2
220 ; CHECK-NEXT: movaps %xmm2, %xmm0
222 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 2>
223 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
224 %or = or <4 x i32> %shuf1, %shuf2
229 define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) {
230 ; CHECK-LABEL: test18:
232 ; CHECK-NEXT: xorps %xmm2, %xmm2
233 ; CHECK-NEXT: xorps %xmm3, %xmm3
234 ; CHECK-NEXT: blendps {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3]
235 ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,0,1,1]
236 ; CHECK-NEXT: blendps {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
237 ; CHECK-NEXT: orps %xmm0, %xmm2
238 ; CHECK-NEXT: movaps %xmm2, %xmm0
240 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 4>
241 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
242 %or = or <4 x i32> %shuf1, %shuf2
247 define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
248 ; CHECK-LABEL: test19:
250 ; CHECK-NEXT: xorps %xmm2, %xmm2
251 ; CHECK-NEXT: xorps %xmm3, %xmm3
252 ; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm0[0,3]
253 ; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,2,1,3]
254 ; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[0,0]
255 ; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,2]
256 ; CHECK-NEXT: orps %xmm3, %xmm2
257 ; CHECK-NEXT: movaps %xmm2, %xmm0
259 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 3>
260 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 2, i32 2>
261 %or = or <4 x i32> %shuf1, %shuf2
266 define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) {
267 ; CHECK-LABEL: test20:
269 ; CHECK-NEXT: orps %xmm1, %xmm0
270 ; CHECK-NEXT: movq %xmm0, %xmm0
272 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
273 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2>
274 %or = or <2 x i64> %shuf1, %shuf2
279 define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
280 ; CHECK-LABEL: test21:
282 ; CHECK-NEXT: orps %xmm1, %xmm0
283 ; CHECK-NEXT: movq %xmm0, %xmm0
284 ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
286 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
287 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0>
288 %or = or <2 x i64> %shuf1, %shuf2
292 ; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle
293 ; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to
294 ; handle legal vector value types.
295 define <4 x i8> @test_crash(<4 x i8> %a, <4 x i8> %b) {
296 ; CHECK-LABEL: test_crash:
298 ; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]
299 ; CHECK-NEXT: movdqa %xmm1, %xmm0
301 %shuf1 = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3>
302 %shuf2 = shufflevector <4 x i8> %b, <4 x i8> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4>
303 %or = or <4 x i8> %shuf1, %shuf2