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Adding intrinsics to the llvm backend for TBM instruction set.
[oota-llvm.git]
/
test
/
CodeGen
/
X86
/
ins_subreg_coalesce-2.ll
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; RUN: llc < %s -march=x86-64 | not grep movw
2
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define i16 @test5(i16 %f12) nounwind {
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%f11 = shl i16 %f12, 2 ; <i16> [#uses=1]
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%tmp7.25 = ashr i16 %f11, 8 ; <i16> [#uses=1]
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ret i16 %tmp7.25
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}