1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE2
3 ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX
5 define <8 x i16> @test1(<8 x i16> %A, <8 x i16> %B) {
7 ; SSE2: # BB#0: # %entry
8 ; SSE2-NEXT: movd %xmm1, %eax
9 ; SSE2-NEXT: movzwl %ax, %eax
10 ; SSE2-NEXT: movd %eax, %xmm1
11 ; SSE2-NEXT: psllw %xmm1, %xmm0
15 ; AVX: # BB#0: # %entry
16 ; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
17 ; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
18 ; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0
21 %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
22 %shl = shl <8 x i16> %A, %vecinit14
26 define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
28 ; SSE2: # BB#0: # %entry
29 ; SSE2-NEXT: xorps %xmm2, %xmm2
30 ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
31 ; SSE2-NEXT: pslld %xmm2, %xmm0
35 ; AVX: # BB#0: # %entry
36 ; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
37 ; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
38 ; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0
41 %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
42 %shl = shl <4 x i32> %A, %vecinit6
46 define <2 x i64> @test3(<2 x i64> %A, <2 x i64> %B) {
48 ; SSE2: # BB#0: # %entry
49 ; SSE2-NEXT: psllq %xmm1, %xmm0
53 ; AVX: # BB#0: # %entry
54 ; AVX-NEXT: vpsllq %xmm1, %xmm0, %xmm0
57 %vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer
58 %shl = shl <2 x i64> %A, %vecinit2
62 define <8 x i16> @test4(<8 x i16> %A, <8 x i16> %B) {
64 ; SSE2: # BB#0: # %entry
65 ; SSE2-NEXT: movd %xmm1, %eax
66 ; SSE2-NEXT: movzwl %ax, %eax
67 ; SSE2-NEXT: movd %eax, %xmm1
68 ; SSE2-NEXT: psrlw %xmm1, %xmm0
72 ; AVX: # BB#0: # %entry
73 ; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
74 ; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
75 ; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
78 %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
79 %shr = lshr <8 x i16> %A, %vecinit14
83 define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) {
85 ; SSE2: # BB#0: # %entry
86 ; SSE2-NEXT: xorps %xmm2, %xmm2
87 ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
88 ; SSE2-NEXT: psrld %xmm2, %xmm0
92 ; AVX: # BB#0: # %entry
93 ; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
94 ; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
95 ; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0
98 %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
99 %shr = lshr <4 x i32> %A, %vecinit6
103 define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) {
105 ; SSE2: # BB#0: # %entry
106 ; SSE2-NEXT: psrlq %xmm1, %xmm0
110 ; AVX: # BB#0: # %entry
111 ; AVX-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
114 %vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer
115 %shr = lshr <2 x i64> %A, %vecinit2
119 define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) {
121 ; SSE2: # BB#0: # %entry
122 ; SSE2-NEXT: movd %xmm1, %eax
123 ; SSE2-NEXT: movzwl %ax, %eax
124 ; SSE2-NEXT: movd %eax, %xmm1
125 ; SSE2-NEXT: psraw %xmm1, %xmm0
129 ; AVX: # BB#0: # %entry
130 ; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
131 ; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
132 ; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0
135 %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
136 %shr = ashr <8 x i16> %A, %vecinit14
140 define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) {
142 ; SSE2: # BB#0: # %entry
143 ; SSE2-NEXT: xorps %xmm2, %xmm2
144 ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
145 ; SSE2-NEXT: psrad %xmm2, %xmm0
149 ; AVX: # BB#0: # %entry
150 ; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
151 ; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
152 ; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0
155 %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
156 %shr = ashr <4 x i32> %A, %vecinit6