1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
2 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
3 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
6 ; Verify that the following shifts are lowered into a sequence of two shifts plus
7 ; a blend. On pre-avx2 targets, instead of scalarizing logical and arithmetic
8 ; packed shift right by a constant build_vector the backend should always try to
9 ; emit a simpler sequence of two shifts + blend when possible.
11 define <8 x i16> @test1(<8 x i16> %a) {
12 %lshr = lshr <8 x i16> %a, <i16 3, i16 3, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
28 define <8 x i16> @test2(<8 x i16> %a) {
29 %lshr = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 2, i16 2, i16 2, i16 2>
45 define <4 x i32> @test3(<4 x i32> %a) {
46 %lshr = lshr <4 x i32> %a, <i32 3, i32 2, i32 2, i32 2>
60 define <4 x i32> @test4(<4 x i32> %a) {
61 %lshr = lshr <4 x i32> %a, <i32 3, i32 3, i32 2, i32 2>
75 define <8 x i16> @test5(<8 x i16> %a) {
76 %lshr = ashr <8 x i16> %a, <i16 3, i16 3, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
80 define <8 x i16> @test6(<8 x i16> %a) {
81 %lshr = ashr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 2, i16 2, i16 2, i16 2>
97 define <4 x i32> @test7(<4 x i32> %a) {
98 %lshr = ashr <4 x i32> %a, <i32 3, i32 2, i32 2, i32 2>
112 define <4 x i32> @test8(<4 x i32> %a) {
113 %lshr = ashr <4 x i32> %a, <i32 3, i32 3, i32 2, i32 2>