1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
3 ; Full strength reduction wouldn't reduce register pressure, so LSR should
4 ; stick with indexing here.
6 ; Also checks andps and andnps shares the same constantpool. Previously llvm
7 ; will codegen two andps, one using 0x80000000, the other 0x7fffffff.
10 ; CHECK: movaps LCPI1_0
11 ; CHECK: movaps LCPI1_1
12 ; CHECK-NOT: movaps LCPI1_2
13 ; CHECK: movaps (%rsi,%rax,4), %xmm2
16 ; CHECK: movaps %xmm2, (%rdi,%rax,4)
17 ; CHECK: addq $4, %rax
18 ; CHECK: cmpl %eax, (%rdx)
21 define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind {
23 %0 = load i32* %n, align 4
24 %1 = icmp sgt i32 %0, 0
25 br i1 %1, label %bb, label %return
28 %indvar = phi i64 [ %indvar.next, %bb ], [ 0, %entry ]
29 %tmp = shl i64 %indvar, 2
30 %scevgep = getelementptr float* %y, i64 %tmp
31 %scevgep9 = bitcast float* %scevgep to <4 x float>*
32 %scevgep10 = getelementptr float* %x, i64 %tmp
33 %scevgep1011 = bitcast float* %scevgep10 to <4 x float>*
34 %2 = load <4 x float>* %scevgep1011, align 16
35 %3 = bitcast <4 x float> %2 to <4 x i32>
36 %4 = and <4 x i32> %3, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
37 %5 = bitcast <4 x i32> %4 to <4 x float>
38 %6 = and <4 x i32> %3, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
39 %7 = tail call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %5, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) nounwind
40 %tmp.i4 = bitcast <4 x float> %7 to <4 x i32>
41 %8 = xor <4 x i32> %tmp.i4, <i32 -1, i32 -1, i32 -1, i32 -1>
42 %9 = and <4 x i32> %8, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>
43 %10 = or <4 x i32> %9, %6
44 %11 = bitcast <4 x i32> %10 to <4 x float>
45 %12 = fadd <4 x float> %2, %11
46 %13 = fsub <4 x float> %12, %11
47 %14 = tail call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %2, <4 x float> %13, i8 1) nounwind
48 %15 = bitcast <4 x float> %14 to <4 x i32>
49 %16 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %15) nounwind readnone
50 %17 = fadd <4 x float> %13, %16
51 %tmp.i = bitcast <4 x float> %17 to <4 x i32>
52 %18 = or <4 x i32> %tmp.i, %6
53 %19 = bitcast <4 x i32> %18 to <4 x float>
54 store <4 x float> %19, <4 x float>* %scevgep9, align 16
55 %tmp12 = add i64 %tmp, 4
56 %tmp13 = trunc i64 %tmp12 to i32
57 %20 = load i32* %n, align 4
58 %21 = icmp sgt i32 %20, %tmp13
59 %indvar.next = add i64 %indvar, 1
60 br i1 %21, label %bb, label %return
66 declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
68 declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone