1 ; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s
3 define i64 @t0(<1 x i64>* %a, i32* %b) {
5 ; CHECK: # BB#0:{{.*}} %entry
6 ; CHECK: movq (%[[REG1:[a-z]+]]), %mm0
7 ; CHECK-NEXT: psllq (%[[REG2:[a-z]+]]), %mm0
8 ; CHECK-NEXT: movd %mm0, %rax
11 %0 = bitcast <1 x i64>* %a to x86_mmx*
12 %1 = load x86_mmx, x86_mmx* %0, align 8
13 %2 = load i32, i32* %b, align 4
14 %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2)
15 %4 = bitcast x86_mmx %3 to i64
18 declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
20 define i64 @t1(<1 x i64>* %a, i32* %b) {
22 ; CHECK: # BB#0:{{.*}} %entry
23 ; CHECK: movq (%[[REG1]]), %mm0
24 ; CHECK-NEXT: psrlq (%[[REG2]]), %mm0
25 ; CHECK-NEXT: movd %mm0, %rax
28 %0 = bitcast <1 x i64>* %a to x86_mmx*
29 %1 = load x86_mmx, x86_mmx* %0, align 8
30 %2 = load i32, i32* %b, align 4
31 %3 = tail call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %1, i32 %2)
32 %4 = bitcast x86_mmx %3 to i64
35 declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32)
37 define i64 @t2(<1 x i64>* %a, i32* %b) {
39 ; CHECK: # BB#0:{{.*}} %entry
40 ; CHECK: movq (%[[REG1]]), %mm0
41 ; CHECK-NEXT: psllw (%[[REG2]]), %mm0
42 ; CHECK-NEXT: movd %mm0, %rax
45 %0 = bitcast <1 x i64>* %a to x86_mmx*
46 %1 = load x86_mmx, x86_mmx* %0, align 8
47 %2 = load i32, i32* %b, align 4
48 %3 = tail call x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx %1, i32 %2)
49 %4 = bitcast x86_mmx %3 to i64
52 declare x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx, i32)
54 define i64 @t3(<1 x i64>* %a, i32* %b) {
56 ; CHECK: # BB#0:{{.*}} %entry
57 ; CHECK: movq (%[[REG1]]), %mm0
58 ; CHECK-NEXT: psrlw (%[[REG2]]), %mm0
59 ; CHECK-NEXT: movd %mm0, %rax
62 %0 = bitcast <1 x i64>* %a to x86_mmx*
63 %1 = load x86_mmx, x86_mmx* %0, align 8
64 %2 = load i32, i32* %b, align 4
65 %3 = tail call x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx %1, i32 %2)
66 %4 = bitcast x86_mmx %3 to i64
69 declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32)
71 define i64 @t4(<1 x i64>* %a, i32* %b) {
73 ; CHECK: # BB#0:{{.*}} %entry
74 ; CHECK: movq (%[[REG1]]), %mm0
75 ; CHECK-NEXT: pslld (%[[REG2]]), %mm0
76 ; CHECK-NEXT: movd %mm0, %rax
79 %0 = bitcast <1 x i64>* %a to x86_mmx*
80 %1 = load x86_mmx, x86_mmx* %0, align 8
81 %2 = load i32, i32* %b, align 4
82 %3 = tail call x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx %1, i32 %2)
83 %4 = bitcast x86_mmx %3 to i64
86 declare x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx, i32)
88 define i64 @t5(<1 x i64>* %a, i32* %b) {
90 ; CHECK: # BB#0:{{.*}} %entry
91 ; CHECK: movq (%[[REG1]]), %mm0
92 ; CHECK-NEXT: psrld (%[[REG2]]), %mm0
93 ; CHECK-NEXT: movd %mm0, %rax
96 %0 = bitcast <1 x i64>* %a to x86_mmx*
97 %1 = load x86_mmx, x86_mmx* %0, align 8
98 %2 = load i32, i32* %b, align 4
99 %3 = tail call x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx %1, i32 %2)
100 %4 = bitcast x86_mmx %3 to i64
103 declare x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx, i32)
105 define i64 @t6(<1 x i64>* %a, i32* %b) {
107 ; CHECK: # BB#0:{{.*}} %entry
108 ; CHECK: movq (%[[REG1]]), %mm0
109 ; CHECK-NEXT: psraw (%[[REG2]]), %mm0
110 ; CHECK-NEXT: movd %mm0, %rax
113 %0 = bitcast <1 x i64>* %a to x86_mmx*
114 %1 = load x86_mmx, x86_mmx* %0, align 8
115 %2 = load i32, i32* %b, align 4
116 %3 = tail call x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx %1, i32 %2)
117 %4 = bitcast x86_mmx %3 to i64
120 declare x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx, i32)
122 define i64 @t7(<1 x i64>* %a, i32* %b) {
124 ; CHECK: # BB#0:{{.*}} %entry
125 ; CHECK: movq (%[[REG1]]), %mm0
126 ; CHECK-NEXT: psrad (%[[REG2]]), %mm0
127 ; CHECK-NEXT: movd %mm0, %rax
130 %0 = bitcast <1 x i64>* %a to x86_mmx*
131 %1 = load x86_mmx, x86_mmx* %0, align 8
132 %2 = load i32, i32* %b, align 4
133 %3 = tail call x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx %1, i32 %2)
134 %4 = bitcast x86_mmx %3 to i64
137 declare x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx, i32)
139 define i64 @tt0(x86_mmx %t, x86_mmx* %q) {
141 ; CHECK: # BB#0:{{.*}} %entry
142 ; CHECK: paddb (%[[REG3:[a-z]+]]), %mm0
143 ; CHECK-NEXT: movd %mm0, %rax
147 %v = load x86_mmx, x86_mmx* %q
148 %u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %v)
149 %s = bitcast x86_mmx %u to i64
150 call void @llvm.x86.mmx.emms()
153 declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
154 declare void @llvm.x86.mmx.emms()
156 define i64 @tt1(x86_mmx %t, x86_mmx* %q) {
158 ; CHECK: # BB#0:{{.*}} %entry
159 ; CHECK: paddw (%[[REG3]]), %mm0
160 ; CHECK-NEXT: movd %mm0, %rax
164 %v = load x86_mmx, x86_mmx* %q
165 %u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %v)
166 %s = bitcast x86_mmx %u to i64
167 call void @llvm.x86.mmx.emms()
170 declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
172 define i64 @tt2(x86_mmx %t, x86_mmx* %q) {
174 ; CHECK: # BB#0:{{.*}} %entry
175 ; CHECK: paddd (%[[REG3]]), %mm0
176 ; CHECK-NEXT: movd %mm0, %rax
180 %v = load x86_mmx, x86_mmx* %q
181 %u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %v)
182 %s = bitcast x86_mmx %u to i64
183 call void @llvm.x86.mmx.emms()
186 declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
188 define i64 @tt3(x86_mmx %t, x86_mmx* %q) {
190 ; CHECK: # BB#0:{{.*}} %entry
191 ; CHECK: paddq (%[[REG3]]), %mm0
192 ; CHECK-NEXT: movd %mm0, %rax
196 %v = load x86_mmx, x86_mmx* %q
197 %u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %v)
198 %s = bitcast x86_mmx %u to i64
199 call void @llvm.x86.mmx.emms()
202 declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
204 define i64 @tt4(x86_mmx %t, x86_mmx* %q) {
206 ; CHECK: # BB#0:{{.*}} %entry
207 ; CHECK: paddusb (%[[REG3]]), %mm0
208 ; CHECK-NEXT: movd %mm0, %rax
212 %v = load x86_mmx, x86_mmx* %q
213 %u = tail call x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx %t, x86_mmx %v)
214 %s = bitcast x86_mmx %u to i64
215 call void @llvm.x86.mmx.emms()
218 declare x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx, x86_mmx)
220 define i64 @tt5(x86_mmx %t, x86_mmx* %q) {
222 ; CHECK: # BB#0:{{.*}} %entry
223 ; CHECK: paddusw (%[[REG3]]), %mm0
224 ; CHECK-NEXT: movd %mm0, %rax
228 %v = load x86_mmx, x86_mmx* %q
229 %u = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %t, x86_mmx %v)
230 %s = bitcast x86_mmx %u to i64
231 call void @llvm.x86.mmx.emms()
234 declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
236 define i64 @tt6(x86_mmx %t, x86_mmx* %q) {
238 ; CHECK: # BB#0:{{.*}} %entry
239 ; CHECK: psrlw (%[[REG3]]), %mm0
240 ; CHECK-NEXT: movd %mm0, %rax
244 %v = load x86_mmx, x86_mmx* %q
245 %u = tail call x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx %t, x86_mmx %v)
246 %s = bitcast x86_mmx %u to i64
247 call void @llvm.x86.mmx.emms()
250 declare x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx, x86_mmx)
252 define i64 @tt7(x86_mmx %t, x86_mmx* %q) {
254 ; CHECK: # BB#0:{{.*}} %entry
255 ; CHECK: psrld (%[[REG3]]), %mm0
256 ; CHECK-NEXT: movd %mm0, %rax
260 %v = load x86_mmx, x86_mmx* %q
261 %u = tail call x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx %t, x86_mmx %v)
262 %s = bitcast x86_mmx %u to i64
263 call void @llvm.x86.mmx.emms()
266 declare x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx, x86_mmx)
268 define i64 @tt8(x86_mmx %t, x86_mmx* %q) {
270 ; CHECK: # BB#0:{{.*}} %entry
271 ; CHECK: psrlq (%[[REG3]]), %mm0
272 ; CHECK-NEXT: movd %mm0, %rax
276 %v = load x86_mmx, x86_mmx* %q
277 %u = tail call x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx %t, x86_mmx %v)
278 %s = bitcast x86_mmx %u to i64
279 call void @llvm.x86.mmx.emms()
282 declare x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx, x86_mmx)