1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
4 ; InstCombine and DAGCombiner transform an 'add' into an 'or'
5 ; if there are no common bits from the incoming operands.
6 ; LEA instruction selection should be able to see through that
7 ; transform and reduce add/shift/or instruction counts.
9 define i32 @or_shift1_and1(i32 %x, i32 %y) {
10 ; CHECK-LABEL: or_shift1_and1:
12 ; CHECK-NEXT: andl $1, %esi
13 ; CHECK-NEXT: leal (%rsi,%rdi,2), %eax
18 %or = or i32 %and, %shl
22 define i32 @or_shift1_and1_swapped(i32 %x, i32 %y) {
23 ; CHECK-LABEL: or_shift1_and1_swapped:
25 ; CHECK-NEXT: andl $1, %esi
26 ; CHECK-NEXT: leal (%rsi,%rdi,2), %eax
31 %or = or i32 %shl, %and
35 define i32 @or_shift2_and1(i32 %x, i32 %y) {
36 ; CHECK-LABEL: or_shift2_and1:
38 ; CHECK-NEXT: andl $1, %esi
39 ; CHECK-NEXT: leal (%rsi,%rdi,4), %eax
44 %or = or i32 %shl, %and
48 define i32 @or_shift3_and1(i32 %x, i32 %y) {
49 ; CHECK-LABEL: or_shift3_and1:
51 ; CHECK-NEXT: andl $1, %esi
52 ; CHECK-NEXT: leal (%rsi,%rdi,8), %eax
57 %or = or i32 %shl, %and
61 define i32 @or_shift3_and7(i32 %x, i32 %y) {
62 ; CHECK-LABEL: or_shift3_and7:
64 ; CHECK-NEXT: andl $7, %esi
65 ; CHECK-NEXT: leal (%rsi,%rdi,8), %eax
70 %or = or i32 %shl, %and
74 ; The shift is too big for an LEA.
76 define i32 @or_shift4_and1(i32 %x, i32 %y) {
77 ; CHECK-LABEL: or_shift4_and1:
79 ; CHECK-NEXT: shll $4, %edi
80 ; CHECK-NEXT: andl $1, %esi
81 ; CHECK-NEXT: leal (%rsi,%rdi), %eax
86 %or = or i32 %shl, %and
90 ; The mask is too big for the shift, so the 'or' isn't equivalent to an 'add'.
92 define i32 @or_shift3_and8(i32 %x, i32 %y) {
93 ; CHECK-LABEL: or_shift3_and8:
95 ; CHECK-NEXT: leal (,%rdi,8), %eax
96 ; CHECK-NEXT: andl $8, %esi
97 ; CHECK-NEXT: orl %esi, %eax
102 %or = or i32 %shl, %and
106 ; 64-bit operands should work too.
108 define i64 @or_shift1_and1_64(i64 %x, i64 %y) {
109 ; CHECK-LABEL: or_shift1_and1_64:
111 ; CHECK-NEXT: andl $1, %esi
112 ; CHECK-NEXT: leaq (%rsi,%rdi,2), %rax
117 %or = or i64 %and, %shl