1 ; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
5 ; This requires physreg joining, %vreg13 is live everywhere:
6 ; 304L %CL<def> = COPY %vreg13:sub_8bit; GR32_ABCD:%vreg13
7 ; 320L %vreg15<def> = COPY %vreg19; GR32:%vreg15 GR32_NOSP:%vreg19
8 ; 336L %vreg15<def> = SAR32rCL %vreg15, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg15
10 ; This test is XFAIL until the register allocator understands trivial physreg
11 ; interference. <rdar://9802098>
13 define void @foo(i32* nocapture %quadrant, i32* nocapture %ptr, i32 %bbSize, i32 %bbStart, i32 %shifts) nounwind ssp {
16 %j.03 = add i32 %bbSize, -1 ; <i32> [#uses=2]
17 %0 = icmp sgt i32 %j.03, -1 ; <i1> [#uses=1]
18 br i1 %0, label %bb.nph, label %return
20 bb.nph: ; preds = %entry
21 %tmp9 = add i32 %bbStart, %bbSize ; <i32> [#uses=1]
22 %tmp10 = add i32 %tmp9, -1 ; <i32> [#uses=1]
25 bb: ; preds = %bb, %bb.nph
27 ; CHECK-NOT: movb {{.*}}l, %cl
29 %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
30 %j.06 = sub i32 %j.03, %indvar ; <i32> [#uses=1]
31 %tmp11 = sub i32 %tmp10, %indvar ; <i32> [#uses=1]
32 %scevgep = getelementptr i32* %ptr, i32 %tmp11 ; <i32*> [#uses=1]
33 %1 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
34 %2 = ashr i32 %j.06, %shifts ; <i32> [#uses=1]
35 %3 = and i32 %2, 65535 ; <i32> [#uses=1]
36 %4 = getelementptr inbounds i32* %quadrant, i32 %1 ; <i32*> [#uses=1]
37 store i32 %3, i32* %4, align 4
38 %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
39 %exitcond = icmp eq i32 %indvar.next, %bbSize ; <i1> [#uses=1]
40 br i1 %exitcond, label %return, label %bb
42 return: ; preds = %bb, %entry