1 ; RUN: llc < %s -mattr=+sha -mtriple=x86_64-unknown-unknown | FileCheck %s
2 ; RUN: not llc < %s -mtriple=x86_64-unknown-unknown
4 declare <4 x i32> @llvm.x86.sha1rnds4(<4 x i32>, <4 x i32>, i8) nounwind readnone
6 define <4 x i32> @test_sha1rnds4rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
8 %0 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %b, i8 3)
10 ; CHECK: test_sha1rnds4rr
11 ; CHECK: sha1rnds4 $3, %xmm1, %xmm0
14 define <4 x i32> @test_sha1rnds4rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
16 %0 = load <4 x i32>* %b
17 %1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)
19 ; CHECK: test_sha1rnds4rm
20 ; CHECK: sha1rnds4 $3, (%rdi), %xmm0
23 declare <4 x i32> @llvm.x86.sha1nexte(<4 x i32>, <4 x i32>) nounwind readnone
25 define <4 x i32> @test_sha1nexterr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
27 %0 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %b)
29 ; CHECK: test_sha1nexterr
30 ; CHECK: sha1nexte %xmm1, %xmm0
33 define <4 x i32> @test_sha1nexterm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
35 %0 = load <4 x i32>* %b
36 %1 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %0)
38 ; CHECK: test_sha1nexterm
39 ; CHECK: sha1nexte (%rdi), %xmm0
42 declare <4 x i32> @llvm.x86.sha1msg1(<4 x i32>, <4 x i32>) nounwind readnone
44 define <4 x i32> @test_sha1msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
46 %0 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %b)
48 ; CHECK: test_sha1msg1rr
49 ; CHECK: sha1msg1 %xmm1, %xmm0
52 define <4 x i32> @test_sha1msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
54 %0 = load <4 x i32>* %b
55 %1 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %0)
57 ; CHECK: test_sha1msg1rm
58 ; CHECK: sha1msg1 (%rdi), %xmm0
61 declare <4 x i32> @llvm.x86.sha1msg2(<4 x i32>, <4 x i32>) nounwind readnone
63 define <4 x i32> @test_sha1msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
65 %0 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %b)
67 ; CHECK: test_sha1msg2rr
68 ; CHECK: sha1msg2 %xmm1, %xmm0
71 define <4 x i32> @test_sha1msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
73 %0 = load <4 x i32>* %b
74 %1 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %0)
76 ; CHECK: test_sha1msg2rm
77 ; CHECK: sha1msg2 (%rdi), %xmm0
80 declare <4 x i32> @llvm.x86.sha256rnds2(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
82 define <4 x i32> @test_sha256rnds2rr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind uwtable {
84 %0 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
86 ; CHECK: test_sha256rnds2rr
87 ; CHECK: movaps %xmm0, [[XMM_TMP1:%xmm[1-9][0-9]?]]
88 ; CHECK: movaps %xmm2, %xmm0
89 ; CHECK: sha256rnds2 %xmm1, [[XMM_TMP1]]
92 define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, <4 x i32>* %b, <4 x i32> %c) nounwind uwtable {
94 %0 = load <4 x i32>* %b
95 %1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c)
97 ; CHECK: test_sha256rnds2rm
98 ; CHECK: movaps %xmm0, [[XMM_TMP2:%xmm[1-9][0-9]?]]
99 ; CHECK: movaps %xmm1, %xmm0
100 ; CHECK: sha256rnds2 (%rdi), [[XMM_TMP2]]
103 declare <4 x i32> @llvm.x86.sha256msg1(<4 x i32>, <4 x i32>) nounwind readnone
105 define <4 x i32> @test_sha256msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
107 %0 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %b)
109 ; CHECK: test_sha256msg1rr
110 ; CHECK: sha256msg1 %xmm1, %xmm0
113 define <4 x i32> @test_sha256msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
115 %0 = load <4 x i32>* %b
116 %1 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %0)
118 ; CHECK: test_sha256msg1rm
119 ; CHECK: sha256msg1 (%rdi), %xmm0
122 declare <4 x i32> @llvm.x86.sha256msg2(<4 x i32>, <4 x i32>) nounwind readnone
124 define <4 x i32> @test_sha256msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
126 %0 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %b)
128 ; CHECK: test_sha256msg2rr
129 ; CHECK: sha256msg2 %xmm1, %xmm0
132 define <4 x i32> @test_sha256msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
134 %0 = load <4 x i32>* %b
135 %1 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %0)
137 ; CHECK: test_sha256msg2rm
138 ; CHECK: sha256msg2 (%rdi), %xmm0