1 ; RUN: llc -mtriple=x86_64-pc-linux -mcpu=corei7 < %s | FileCheck -check-prefix=CHECK -check-prefix=SSE2 %s
2 ; RUN: llc -mtriple=x86_64-pc-linux -mattr=-sse4.1 -mcpu=corei7 < %s | FileCheck -check-prefix=CHECK -check-prefix=SSE2 %s
3 ; RUN: llc -mtriple=x86_64-pc-linux -mcpu=corei7-avx < %s | FileCheck -check-prefix=CHECK -check-prefix=AVX %s
5 ; Ensure that the backend selects SSE/AVX scalar fp instructions
6 ; from a packed fp instrution plus a vector insert.
9 define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
10 %1 = fadd <4 x float> %a, %b
11 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
15 ; CHECK-LABEL: test_add_ss
16 ; SSE2: addss %xmm1, %xmm0
17 ; AVX: vaddss %xmm1, %xmm0, %xmm0
22 define <4 x float> @test_sub_ss(<4 x float> %a, <4 x float> %b) {
23 %1 = fsub <4 x float> %a, %b
24 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
28 ; CHECK-LABEL: test_sub_ss
29 ; SSE2: subss %xmm1, %xmm0
30 ; AVX: vsubss %xmm1, %xmm0, %xmm0
35 define <4 x float> @test_mul_ss(<4 x float> %a, <4 x float> %b) {
36 %1 = fmul <4 x float> %a, %b
37 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
41 ; CHECK-LABEL: test_mul_ss
42 ; SSE2: mulss %xmm1, %xmm0
43 ; AVX: vmulss %xmm1, %xmm0, %xmm0
48 define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {
49 %1 = fdiv <4 x float> %a, %b
50 %2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
54 ; CHECK-LABEL: test_div_ss
55 ; SSE2: divss %xmm1, %xmm0
56 ; AVX: vdivss %xmm1, %xmm0, %xmm0
61 define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
62 %1 = fadd <2 x double> %a, %b
63 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>
67 ; CHECK-LABEL: test_add_sd
68 ; SSE2: addsd %xmm1, %xmm0
69 ; AVX: vaddsd %xmm1, %xmm0, %xmm0
74 define <2 x double> @test_sub_sd(<2 x double> %a, <2 x double> %b) {
75 %1 = fsub <2 x double> %a, %b
76 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>
80 ; CHECK-LABEL: test_sub_sd
81 ; SSE2: subsd %xmm1, %xmm0
82 ; AVX: vsubsd %xmm1, %xmm0, %xmm0
87 define <2 x double> @test_mul_sd(<2 x double> %a, <2 x double> %b) {
88 %1 = fmul <2 x double> %a, %b
89 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>
93 ; CHECK-LABEL: test_mul_sd
94 ; SSE2: mulsd %xmm1, %xmm0
95 ; AVX: vmulsd %xmm1, %xmm0, %xmm0
100 define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
101 %1 = fdiv <2 x double> %a, %b
102 %2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>
106 ; CHECK-LABEL: test_div_sd
107 ; SSE2: divsd %xmm1, %xmm0
108 ; AVX: vdivsd %xmm1, %xmm0, %xmm0
113 define <4 x float> @test2_add_ss(<4 x float> %a, <4 x float> %b) {
114 %1 = fadd <4 x float> %b, %a
115 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
119 ; CHECK-LABEL: test2_add_ss
120 ; SSE2: addss %xmm0, %xmm1
121 ; AVX: vaddss %xmm0, %xmm1, %xmm0
126 define <4 x float> @test2_sub_ss(<4 x float> %a, <4 x float> %b) {
127 %1 = fsub <4 x float> %b, %a
128 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
132 ; CHECK-LABEL: test2_sub_ss
133 ; SSE2: subss %xmm0, %xmm1
134 ; AVX: vsubss %xmm0, %xmm1, %xmm0
139 define <4 x float> @test2_mul_ss(<4 x float> %a, <4 x float> %b) {
140 %1 = fmul <4 x float> %b, %a
141 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
145 ; CHECK-LABEL: test2_mul_ss
146 ; SSE2: mulss %xmm0, %xmm1
147 ; AVX: vmulss %xmm0, %xmm1, %xmm0
152 define <4 x float> @test2_div_ss(<4 x float> %a, <4 x float> %b) {
153 %1 = fdiv <4 x float> %b, %a
154 %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
158 ; CHECK-LABEL: test2_div_ss
159 ; SSE2: divss %xmm0, %xmm1
160 ; AVX: vdivss %xmm0, %xmm1, %xmm0
165 define <2 x double> @test2_add_sd(<2 x double> %a, <2 x double> %b) {
166 %1 = fadd <2 x double> %b, %a
167 %2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>
171 ; CHECK-LABEL: test2_add_sd
172 ; SSE2: addsd %xmm0, %xmm1
173 ; AVX: vaddsd %xmm0, %xmm1, %xmm0
178 define <2 x double> @test2_sub_sd(<2 x double> %a, <2 x double> %b) {
179 %1 = fsub <2 x double> %b, %a
180 %2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>
184 ; CHECK-LABEL: test2_sub_sd
185 ; SSE2: subsd %xmm0, %xmm1
186 ; AVX: vsubsd %xmm0, %xmm1, %xmm0
191 define <2 x double> @test2_mul_sd(<2 x double> %a, <2 x double> %b) {
192 %1 = fmul <2 x double> %b, %a
193 %2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>
197 ; CHECK-LABEL: test2_mul_sd
198 ; SSE2: mulsd %xmm0, %xmm1
199 ; AVX: vmulsd %xmm0, %xmm1, %xmm0
204 define <2 x double> @test2_div_sd(<2 x double> %a, <2 x double> %b) {
205 %1 = fdiv <2 x double> %b, %a
206 %2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>
210 ; CHECK-LABEL: test2_div_sd
211 ; SSE2: divsd %xmm0, %xmm1
212 ; AVX: vdivsd %xmm0, %xmm1, %xmm0