1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 -mcpu=corei7 | FileCheck %s
3 ; SSE2 Logical Shift Left
5 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
7 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
11 ; CHECK-LABEL: test_sllw_1:
12 ; CHECK: psllw $0, %xmm0
15 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
17 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
21 ; CHECK-LABEL: test_sllw_2:
22 ; CHECK: paddw %xmm0, %xmm0
25 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
27 %shl = shl <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
31 ; CHECK-LABEL: test_sllw_3:
32 ; CHECK: xorps %xmm0, %xmm0
35 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
37 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
41 ; CHECK-LABEL: test_slld_1:
42 ; CHECK: pslld $0, %xmm0
45 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
47 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
51 ; CHECK-LABEL: test_slld_2:
52 ; CHECK: paddd %xmm0, %xmm0
55 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
57 %shl = shl <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32>
61 ; CHECK-LABEL: test_slld_3:
62 ; CHECK: xorps %xmm0, %xmm0
65 define <2 x i64> @test_sllq_1(<2 x i64> %InVec) {
67 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
71 ; CHECK-LABEL: test_sllq_1:
72 ; CHECK: psllq $0, %xmm0
75 define <2 x i64> @test_sllq_2(<2 x i64> %InVec) {
77 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
81 ; CHECK-LABEL: test_sllq_2:
82 ; CHECK: paddq %xmm0, %xmm0
85 define <2 x i64> @test_sllq_3(<2 x i64> %InVec) {
87 %shl = shl <2 x i64> %InVec, <i64 64, i64 64>
91 ; CHECK-LABEL: test_sllq_3:
92 ; CHECK: xorps %xmm0, %xmm0
95 ; SSE2 Arithmetic Shift
97 define <8 x i16> @test_sraw_1(<8 x i16> %InVec) {
99 %shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
103 ; CHECK-LABEL: test_sraw_1:
104 ; CHECK: psraw $0, %xmm0
107 define <8 x i16> @test_sraw_2(<8 x i16> %InVec) {
109 %shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
113 ; CHECK-LABEL: test_sraw_2:
114 ; CHECK: psraw $1, %xmm0
117 define <8 x i16> @test_sraw_3(<8 x i16> %InVec) {
119 %shl = ashr <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
123 ; CHECK-LABEL: test_sraw_3:
124 ; CHECK: psraw $16, %xmm0
127 define <4 x i32> @test_srad_1(<4 x i32> %InVec) {
129 %shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
133 ; CHECK-LABEL: test_srad_1:
134 ; CHECK: psrad $0, %xmm0
137 define <4 x i32> @test_srad_2(<4 x i32> %InVec) {
139 %shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
143 ; CHECK-LABEL: test_srad_2:
144 ; CHECK: psrad $1, %xmm0
147 define <4 x i32> @test_srad_3(<4 x i32> %InVec) {
149 %shl = ashr <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32>
153 ; CHECK-LABEL: test_srad_3:
154 ; CHECK: psrad $32, %xmm0
157 ; SSE Logical Shift Right
159 define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {
161 %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
165 ; CHECK-LABEL: test_srlw_1:
166 ; CHECK: psrlw $0, %xmm0
169 define <8 x i16> @test_srlw_2(<8 x i16> %InVec) {
171 %shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
175 ; CHECK-LABEL: test_srlw_2:
176 ; CHECK: psrlw $1, %xmm0
179 define <8 x i16> @test_srlw_3(<8 x i16> %InVec) {
181 %shl = lshr <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
185 ; CHECK-LABEL: test_srlw_3:
186 ; CHECK: xorps %xmm0, %xmm0
189 define <4 x i32> @test_srld_1(<4 x i32> %InVec) {
191 %shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
195 ; CHECK-LABEL: test_srld_1:
196 ; CHECK: psrld $0, %xmm0
199 define <4 x i32> @test_srld_2(<4 x i32> %InVec) {
201 %shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
205 ; CHECK-LABEL: test_srld_2:
206 ; CHECK: psrld $1, %xmm0
209 define <4 x i32> @test_srld_3(<4 x i32> %InVec) {
211 %shl = lshr <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32>
215 ; CHECK-LABEL: test_srld_3:
216 ; CHECK: xorps %xmm0, %xmm0
219 define <2 x i64> @test_srlq_1(<2 x i64> %InVec) {
221 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
225 ; CHECK-LABEL: test_srlq_1:
226 ; CHECK: psrlq $0, %xmm0
229 define <2 x i64> @test_srlq_2(<2 x i64> %InVec) {
231 %shl = lshr <2 x i64> %InVec, <i64 1, i64 1>
235 ; CHECK-LABEL: test_srlq_2:
236 ; CHECK: psrlq $1, %xmm0
239 define <2 x i64> @test_srlq_3(<2 x i64> %InVec) {
241 %shl = lshr <2 x i64> %InVec, <i64 64, i64 64>
245 ; CHECK-LABEL: test_srlq_3:
246 ; CHECK: xorps %xmm0, %xmm0