1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 | FileCheck %s
3 ; SSE2 Logical Shift Left
5 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
7 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
11 ; CHECK-LABEL: test_sllw_1:
12 ; CHECK-NOT: psllw $0, %xmm0
15 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
17 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
21 ; CHECK-LABEL: test_sllw_2:
22 ; CHECK: paddw %xmm0, %xmm0
25 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
27 %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
31 ; CHECK-LABEL: test_sllw_3:
32 ; CHECK: psllw $15, %xmm0
35 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
37 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
41 ; CHECK-LABEL: test_slld_1:
42 ; CHECK-NOT: pslld $0, %xmm0
45 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
47 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
51 ; CHECK-LABEL: test_slld_2:
52 ; CHECK: paddd %xmm0, %xmm0
55 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
57 %shl = shl <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
61 ; CHECK-LABEL: test_slld_3:
62 ; CHECK: pslld $31, %xmm0
65 define <2 x i64> @test_sllq_1(<2 x i64> %InVec) {
67 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
71 ; CHECK-LABEL: test_sllq_1:
72 ; CHECK-NOT: psllq $0, %xmm0
75 define <2 x i64> @test_sllq_2(<2 x i64> %InVec) {
77 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
81 ; CHECK-LABEL: test_sllq_2:
82 ; CHECK: paddq %xmm0, %xmm0
85 define <2 x i64> @test_sllq_3(<2 x i64> %InVec) {
87 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
91 ; CHECK-LABEL: test_sllq_3:
92 ; CHECK: psllq $63, %xmm0
95 ; SSE2 Arithmetic Shift
97 define <8 x i16> @test_sraw_1(<8 x i16> %InVec) {
99 %shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
103 ; CHECK-LABEL: test_sraw_1:
104 ; CHECK-NOT: psraw $0, %xmm0
107 define <8 x i16> @test_sraw_2(<8 x i16> %InVec) {
109 %shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
113 ; CHECK-LABEL: test_sraw_2:
114 ; CHECK: psraw $1, %xmm0
117 define <8 x i16> @test_sraw_3(<8 x i16> %InVec) {
119 %shl = ashr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
123 ; CHECK-LABEL: test_sraw_3:
124 ; CHECK: psraw $15, %xmm0
127 define <4 x i32> @test_srad_1(<4 x i32> %InVec) {
129 %shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
133 ; CHECK-LABEL: test_srad_1:
134 ; CHECK-NOT: psrad $0, %xmm0
137 define <4 x i32> @test_srad_2(<4 x i32> %InVec) {
139 %shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
143 ; CHECK-LABEL: test_srad_2:
144 ; CHECK: psrad $1, %xmm0
147 define <4 x i32> @test_srad_3(<4 x i32> %InVec) {
149 %shl = ashr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
153 ; CHECK-LABEL: test_srad_3:
154 ; CHECK: psrad $31, %xmm0
157 ; SSE Logical Shift Right
159 define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {
161 %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
165 ; CHECK-LABEL: test_srlw_1:
166 ; CHECK-NOT: psrlw $0, %xmm0
169 define <8 x i16> @test_srlw_2(<8 x i16> %InVec) {
171 %shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
175 ; CHECK-LABEL: test_srlw_2:
176 ; CHECK: psrlw $1, %xmm0
179 define <8 x i16> @test_srlw_3(<8 x i16> %InVec) {
181 %shl = lshr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
185 ; CHECK-LABEL: test_srlw_3:
186 ; CHECK: psrlw $15, %xmm0
189 define <4 x i32> @test_srld_1(<4 x i32> %InVec) {
191 %shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
195 ; CHECK-LABEL: test_srld_1:
196 ; CHECK-NOT: psrld $0, %xmm0
199 define <4 x i32> @test_srld_2(<4 x i32> %InVec) {
201 %shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
205 ; CHECK-LABEL: test_srld_2:
206 ; CHECK: psrld $1, %xmm0
209 define <4 x i32> @test_srld_3(<4 x i32> %InVec) {
211 %shl = lshr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
215 ; CHECK-LABEL: test_srld_3:
216 ; CHECK: psrld $31, %xmm0
219 define <2 x i64> @test_srlq_1(<2 x i64> %InVec) {
221 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
225 ; CHECK-LABEL: test_srlq_1:
226 ; CHECK-NOT: psrlq $0, %xmm0
229 define <2 x i64> @test_srlq_2(<2 x i64> %InVec) {
231 %shl = lshr <2 x i64> %InVec, <i64 1, i64 1>
235 ; CHECK-LABEL: test_srlq_2:
236 ; CHECK: psrlq $1, %xmm0
239 define <2 x i64> @test_srlq_3(<2 x i64> %InVec) {
241 %shl = lshr <2 x i64> %InVec, <i64 63, i64 63>
245 ; CHECK-LABEL: test_srlq_3:
246 ; CHECK: psrlq $63, %xmm0
250 ; CHECK-LABEL: sra_sra_v4i32:
251 ; CHECK: psrad $6, %xmm0
253 define <4 x i32> @sra_sra_v4i32(<4 x i32> %x) nounwind {
254 %sra0 = ashr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
255 %sra1 = ashr <4 x i32> %sra0, <i32 4, i32 4, i32 4, i32 4>
259 ; CHECK-LABEL: @srl_srl_v4i32
260 ; CHECK: psrld $6, %xmm0
262 define <4 x i32> @srl_srl_v4i32(<4 x i32> %x) nounwind {
263 %srl0 = lshr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
264 %srl1 = lshr <4 x i32> %srl0, <i32 4, i32 4, i32 4, i32 4>
268 ; CHECK-LABEL: @srl_shl_v4i32
271 define <4 x i32> @srl_shl_v4i32(<4 x i32> %x) nounwind {
272 %srl0 = shl <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
273 %srl1 = lshr <4 x i32> %srl0, <i32 4, i32 4, i32 4, i32 4>
277 ; CHECK-LABEL: @srl_sra_31_v4i32
278 ; CHECK: psrld $31, %xmm0
280 define <4 x i32> @srl_sra_31_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
281 %sra = ashr <4 x i32> %x, %y
282 %srl1 = lshr <4 x i32> %sra, <i32 31, i32 31, i32 31, i32 31>
286 ; CHECK-LABEL: @shl_shl_v4i32
287 ; CHECK: pslld $6, %xmm0
289 define <4 x i32> @shl_shl_v4i32(<4 x i32> %x) nounwind {
290 %shl0 = shl <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
291 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
295 ; CHECK-LABEL: @shl_sra_v4i32
298 define <4 x i32> @shl_sra_v4i32(<4 x i32> %x) nounwind {
299 %shl0 = ashr <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
300 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
304 ; CHECK-LABEL: @shl_srl_v4i32
305 ; CHECK: pslld $3, %xmm0
308 define <4 x i32> @shl_srl_v4i32(<4 x i32> %x) nounwind {
309 %shl0 = lshr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
310 %shl1 = shl <4 x i32> %shl0, <i32 5, i32 5, i32 5, i32 5>
314 ; CHECK-LABEL: @shl_zext_srl_v4i32
317 define <4 x i32> @shl_zext_srl_v4i32(<4 x i16> %x) nounwind {
318 %srl = lshr <4 x i16> %x, <i16 2, i16 2, i16 2, i16 2>
319 %zext = zext <4 x i16> %srl to <4 x i32>
320 %shl = shl <4 x i32> %zext, <i32 2, i32 2, i32 2, i32 2>
324 ; CHECK: @sra_trunc_srl_v4i32
325 ; CHECK: psrad $19, %xmm0
327 define <4 x i16> @sra_trunc_srl_v4i32(<4 x i32> %x) nounwind {
328 %srl = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
329 %trunc = trunc <4 x i32> %srl to <4 x i16>
330 %sra = ashr <4 x i16> %trunc, <i16 3, i16 3, i16 3, i16 3>
334 ; CHECK-LABEL: @shl_zext_shl_v4i32
336 ; CHECK-NEXT: pslld $19, %xmm0
338 define <4 x i32> @shl_zext_shl_v4i32(<4 x i16> %x) nounwind {
339 %shl0 = shl <4 x i16> %x, <i16 2, i16 2, i16 2, i16 2>
340 %ext = zext <4 x i16> %shl0 to <4 x i32>
341 %shl1 = shl <4 x i32> %ext, <i32 17, i32 17, i32 17, i32 17>
345 ; CHECK-LABEL: @sra_v4i32
346 ; CHECK: psrad $3, %xmm0
348 define <4 x i32> @sra_v4i32(<4 x i32> %x) nounwind {
349 %sra = ashr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
353 ; CHECK-LABEL: @srl_v4i32
354 ; CHECK: psrld $3, %xmm0
356 define <4 x i32> @srl_v4i32(<4 x i32> %x) nounwind {
357 %sra = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
361 ; CHECK-LABEL: @shl_v4i32
362 ; CHECK: pslld $3, %xmm0
364 define <4 x i32> @shl_v4i32(<4 x i32> %x) nounwind {
365 %sra = shl <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>