1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
3 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
5 define <8 x i16> @test_llvm_x86_sse41_pmovsxbw(<16 x i8>* %a) {
6 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbw:
8 ; SSE41-NEXT: pmovsxbw (%rdi), %xmm0
11 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxbw:
13 ; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
15 %1 = load <16 x i8>, <16 x i8>* %a, align 1
16 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
17 %3 = sext <8 x i8> %2 to <8 x i16>
21 define <4 x i32> @test_llvm_x86_sse41_pmovsxbd(<16 x i8>* %a) {
22 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbd:
24 ; SSE41-NEXT: pmovsxbd (%rdi), %xmm0
27 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxbd:
29 ; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
31 %1 = load <16 x i8>, <16 x i8>* %a, align 1
32 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
33 %3 = sext <4 x i8> %2 to <4 x i32>
37 define <2 x i64> @test_llvm_x86_sse41_pmovsxbq(<16 x i8>* %a) {
38 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbq:
40 ; SSE41-NEXT: pmovsxbq (%rdi), %xmm0
43 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxbq:
45 ; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
47 %1 = load <16 x i8>, <16 x i8>* %a, align 1
48 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
49 %3 = sext <2 x i8> %2 to <2 x i64>
53 define <4 x i32> @test_llvm_x86_sse41_pmovsxwd(<8 x i16>* %a) {
54 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwd:
56 ; SSE41-NEXT: pmovsxwd (%rdi), %xmm0
59 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxwd:
61 ; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
63 %1 = load <8 x i16>, <8 x i16>* %a, align 1
64 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
65 %3 = sext <4 x i16> %2 to <4 x i32>
69 define <2 x i64> @test_llvm_x86_sse41_pmovsxwq(<8 x i16>* %a) {
70 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwq:
72 ; SSE41-NEXT: pmovsxwq (%rdi), %xmm0
75 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxwq:
77 ; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
79 %1 = load <8 x i16>, <8 x i16>* %a, align 1
80 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
81 %3 = sext <2 x i16> %2 to <2 x i64>
85 define <2 x i64> @test_llvm_x86_sse41_pmovsxdq(<4 x i32>* %a) {
86 ; SSE41-LABEL: test_llvm_x86_sse41_pmovsxdq:
88 ; SSE41-NEXT: pmovsxdq (%rdi), %xmm0
91 ; AVX-LABEL: test_llvm_x86_sse41_pmovsxdq:
93 ; AVX-NEXT: vpmovsxdq (%rdi), %xmm0
95 %1 = load <4 x i32>, <4 x i32>* %a, align 1
96 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
97 %3 = sext <2 x i32> %2 to <2 x i64>
101 define <8 x i16> @test_llvm_x86_sse41_pmovzxbw(<16 x i8>* %a) {
102 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbw:
104 ; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
107 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxbw:
109 ; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
111 %1 = load <16 x i8>, <16 x i8>* %a, align 1
112 %2 = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %1)
116 define <4 x i32> @test_llvm_x86_sse41_pmovzxbd(<16 x i8>* %a) {
117 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbd:
119 ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
122 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxbd:
124 ; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
126 %1 = load <16 x i8>, <16 x i8>* %a, align 1
127 %2 = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %1)
131 define <2 x i64> @test_llvm_x86_sse41_pmovzxbq(<16 x i8>* %a) {
132 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbq:
134 ; SSE41-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
137 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxbq:
139 ; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
141 %1 = load <16 x i8>, <16 x i8>* %a, align 1
142 %2 = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %1)
146 define <4 x i32> @test_llvm_x86_sse41_pmovzxwd(<8 x i16>* %a) {
147 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwd:
149 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
152 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxwd:
154 ; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
156 %1 = load <8 x i16>, <8 x i16>* %a, align 1
157 %2 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %1)
161 define <2 x i64> @test_llvm_x86_sse41_pmovzxwq(<8 x i16>* %a) {
162 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwq:
164 ; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
167 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxwq:
169 ; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
171 %1 = load <8 x i16>, <8 x i16>* %a, align 1
172 %2 = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %1)
176 define <2 x i64> @test_llvm_x86_sse41_pmovzxdq(<4 x i32>* %a) {
177 ; SSE41-LABEL: test_llvm_x86_sse41_pmovzxdq:
179 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
182 ; AVX-LABEL: test_llvm_x86_sse41_pmovzxdq:
184 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
186 %1 = load <4 x i32>, <4 x i32>* %a, align 1
187 %2 = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %1)
191 declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>)
192 declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>)
193 declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>)
194 declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>)
195 declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>)
196 declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>)