1 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s --check-prefix=X32
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s --check-prefix=X64
4 @g16 = external global i16
6 define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
9 ; X32-NEXT: pinsrd $1, {{[0-9]+}}(%esp), %xmm0
12 ; X64-LABEL: pinsrd_1:
14 ; X64-NEXT: pinsrd $1, %edi, %xmm0
16 %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
20 define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
21 ; X32-LABEL: pinsrb_1:
23 ; X32-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0
26 ; X64-LABEL: pinsrb_1:
28 ; X64-NEXT: pinsrb $1, %edi, %xmm0
30 %tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
34 define <2 x i64> @pmovsxbd_1(i32* %p) nounwind {
35 ; X32-LABEL: pmovsxbd_1:
36 ; X32: ## BB#0: ## %entry
37 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
38 ; X32-NEXT: pmovsxbd (%eax), %xmm0
41 ; X64-LABEL: pmovsxbd_1:
42 ; X64: ## BB#0: ## %entry
43 ; X64-NEXT: pmovsxbd (%rdi), %xmm0
46 %0 = load i32* %p, align 4
47 %1 = insertelement <4 x i32> undef, i32 %0, i32 0
48 %2 = insertelement <4 x i32> %1, i32 0, i32 1
49 %3 = insertelement <4 x i32> %2, i32 0, i32 2
50 %4 = insertelement <4 x i32> %3, i32 0, i32 3
51 %5 = bitcast <4 x i32> %4 to <16 x i8>
52 %6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone
53 %7 = bitcast <4 x i32> %6 to <2 x i64>
57 define <2 x i64> @pmovsxwd_1(i64* %p) nounwind readonly {
58 ; X32-LABEL: pmovsxwd_1:
59 ; X32: ## BB#0: ## %entry
60 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
61 ; X32-NEXT: pmovsxwd (%eax), %xmm0
64 ; X64-LABEL: pmovsxwd_1:
65 ; X64: ## BB#0: ## %entry
66 ; X64-NEXT: pmovsxwd (%rdi), %xmm0
69 %0 = load i64* %p ; <i64> [#uses=1]
70 %tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0 ; <<2 x i64>> [#uses=1]
71 %1 = bitcast <2 x i64> %tmp2 to <8 x i16> ; <<8 x i16>> [#uses=1]
72 %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
73 %3 = bitcast <4 x i32> %2 to <2 x i64> ; <<2 x i64>> [#uses=1]
77 define <2 x i64> @pmovzxbq_1() nounwind {
78 ; X32-LABEL: pmovzxbq_1:
79 ; X32: ## BB#0: ## %entry
80 ; X32-NEXT: movl L_g16$non_lazy_ptr, %eax
81 ; X32-NEXT: pmovzxbq (%eax), %xmm0
84 ; X64-LABEL: pmovzxbq_1:
85 ; X64: ## BB#0: ## %entry
86 ; X64-NEXT: movq _g16@{{.*}}(%rip), %rax
87 ; X64-NEXT: pmovzxbq (%rax), %xmm0
90 %0 = load i16* @g16, align 2 ; <i16> [#uses=1]
91 %1 = insertelement <8 x i16> undef, i16 %0, i32 0 ; <<8 x i16>> [#uses=1]
92 %2 = bitcast <8 x i16> %1 to <16 x i8> ; <<16 x i8>> [#uses=1]
93 %3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
97 declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
98 declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
99 declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
101 define i32 @extractps_1(<4 x float> %v) nounwind {
102 ; X32-LABEL: extractps_1:
104 ; X32-NEXT: extractps $3, %xmm0, %eax
107 ; X64-LABEL: extractps_1:
109 ; X64-NEXT: extractps $3, %xmm0, %eax
111 %s = extractelement <4 x float> %v, i32 3
112 %i = bitcast float %s to i32
115 define i32 @extractps_2(<4 x float> %v) nounwind {
116 ; X32-LABEL: extractps_2:
118 ; X32-NEXT: extractps $3, %xmm0, %eax
121 ; X64-LABEL: extractps_2:
123 ; X64-NEXT: extractps $3, %xmm0, %eax
125 %t = bitcast <4 x float> %v to <4 x i32>
126 %s = extractelement <4 x i32> %t, i32 3
131 ; The non-store form of extractps puts its result into a GPR.
132 ; This makes it suitable for an extract from a <4 x float> that
133 ; is bitcasted to i32, but unsuitable for much of anything else.
135 define float @ext_1(<4 x float> %v) nounwind {
138 ; X32-NEXT: pushl %eax
139 ; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
140 ; X32-NEXT: addss LCPI7_0, %xmm0
141 ; X32-NEXT: movss %xmm0, (%esp)
142 ; X32-NEXT: flds (%esp)
143 ; X32-NEXT: popl %eax
148 ; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
149 ; X64-NEXT: addss {{.*}}(%rip), %xmm0
151 %s = extractelement <4 x float> %v, i32 3
152 %t = fadd float %s, 1.0
155 define float @ext_2(<4 x float> %v) nounwind {
158 ; X32-NEXT: pushl %eax
159 ; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
160 ; X32-NEXT: movss %xmm0, (%esp)
161 ; X32-NEXT: flds (%esp)
162 ; X32-NEXT: popl %eax
167 ; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
169 %s = extractelement <4 x float> %v, i32 3
172 define i32 @ext_3(<4 x i32> %v) nounwind {
175 ; X32-NEXT: pextrd $3, %xmm0, %eax
180 ; X64-NEXT: pextrd $3, %xmm0, %eax
182 %i = extractelement <4 x i32> %v, i32 3
186 define <4 x float> @insertps_1(<4 x float> %t1, <4 x float> %t2) nounwind {
187 ; X32-LABEL: insertps_1:
189 ; X32-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1,2,3]
192 ; X64-LABEL: insertps_1:
194 ; X64-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1,2,3]
196 %tmp1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %t1, <4 x float> %t2, i32 1) nounwind readnone
197 ret <4 x float> %tmp1
200 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
202 define <4 x float> @insertps_2(<4 x float> %t1, float %t2) nounwind {
203 ; X32-LABEL: insertps_2:
205 ; X32-NEXT: insertps $0, {{[0-9]+}}(%esp), %xmm0
208 ; X64-LABEL: insertps_2:
210 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
212 %tmp1 = insertelement <4 x float> %t1, float %t2, i32 0
213 ret <4 x float> %tmp1
215 define <4 x float> @insertps_3(<4 x float> %t1, <4 x float> %t2) nounwind {
216 ; X32-LABEL: insertps_3:
218 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
221 ; X64-LABEL: insertps_3:
223 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
225 %tmp2 = extractelement <4 x float> %t2, i32 0
226 %tmp1 = insertelement <4 x float> %t1, float %tmp2, i32 0
227 ret <4 x float> %tmp1
230 define i32 @ptestz_1(<2 x i64> %t1, <2 x i64> %t2) nounwind {
231 ; X32-LABEL: ptestz_1:
233 ; X32-NEXT: ptest %xmm1, %xmm0
235 ; X32-NEXT: movzbl %al, %eax
238 ; X64-LABEL: ptestz_1:
240 ; X64-NEXT: ptest %xmm1, %xmm0
242 ; X64-NEXT: movzbl %al, %eax
244 %tmp1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
248 define i32 @ptestz_2(<2 x i64> %t1, <2 x i64> %t2) nounwind {
249 ; X32-LABEL: ptestz_2:
251 ; X32-NEXT: ptest %xmm1, %xmm0
252 ; X32-NEXT: sbbl %eax, %eax
253 ; X32-NEXT: andl $1, %eax
256 ; X64-LABEL: ptestz_2:
258 ; X64-NEXT: ptest %xmm1, %xmm0
259 ; X64-NEXT: sbbl %eax, %eax
260 ; X64-NEXT: andl $1, %eax
262 %tmp1 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
266 define i32 @ptestz_3(<2 x i64> %t1, <2 x i64> %t2) nounwind {
267 ; X32-LABEL: ptestz_3:
269 ; X32-NEXT: ptest %xmm1, %xmm0
271 ; X32-NEXT: movzbl %al, %eax
274 ; X64-LABEL: ptestz_3:
276 ; X64-NEXT: ptest %xmm1, %xmm0
278 ; X64-NEXT: movzbl %al, %eax
280 %tmp1 = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
285 declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
286 declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
287 declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
289 ; This used to compile to insertps $0 + insertps $16. insertps $0 is always
291 define <2 x float> @buildvector(<2 x float> %A, <2 x float> %B) nounwind {
292 ; X32-LABEL: buildvector:
293 ; X32: ## BB#0: ## %entry
294 ; X32-NEXT: movaps %xmm0, %xmm2
295 ; X32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
296 ; X32-NEXT: addss %xmm1, %xmm0
297 ; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
298 ; X32-NEXT: addss %xmm2, %xmm1
299 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
302 ; X64-LABEL: buildvector:
303 ; X64: ## BB#0: ## %entry
304 ; X64-NEXT: movaps %xmm0, %xmm2
305 ; X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
306 ; X64-NEXT: addss %xmm1, %xmm0
307 ; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
308 ; X64-NEXT: addss %xmm2, %xmm1
309 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
312 %tmp7 = extractelement <2 x float> %A, i32 0
313 %tmp5 = extractelement <2 x float> %A, i32 1
314 %tmp3 = extractelement <2 x float> %B, i32 0
315 %tmp1 = extractelement <2 x float> %B, i32 1
316 %add.r = fadd float %tmp7, %tmp3
317 %add.i = fadd float %tmp5, %tmp1
318 %tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
319 %tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
320 ret <2 x float> %tmp9
323 define <4 x float> @insertps_from_shufflevector_1(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
324 ; X32-LABEL: insertps_from_shufflevector_1:
325 ; X32: ## BB#0: ## %entry
326 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
327 ; X32-NEXT: insertps $48, (%eax), %xmm0
330 ; X64-LABEL: insertps_from_shufflevector_1:
331 ; X64: ## BB#0: ## %entry
332 ; X64-NEXT: insertps $48, (%rdi), %xmm0
335 %0 = load <4 x float>* %pb, align 16
336 %vecinit6 = shufflevector <4 x float> %a, <4 x float> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
337 ret <4 x float> %vecinit6
340 define <4 x float> @insertps_from_shufflevector_2(<4 x float> %a, <4 x float> %b) {
341 ; X32-LABEL: insertps_from_shufflevector_2:
342 ; X32: ## BB#0: ## %entry
343 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1],xmm0[3]
346 ; X64-LABEL: insertps_from_shufflevector_2:
347 ; X64: ## BB#0: ## %entry
348 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1],xmm0[3]
351 %vecinit6 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
352 ret <4 x float> %vecinit6
355 ; For loading an i32 from memory into an xmm register we use pinsrd
356 ; instead of insertps
357 define <4 x i32> @pinsrd_from_shufflevector_i32(<4 x i32> %a, <4 x i32>* nocapture readonly %pb) {
358 ; X32-LABEL: pinsrd_from_shufflevector_i32:
359 ; X32: ## BB#0: ## %entry
360 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
361 ; X32-NEXT: insertps $48, (%eax), %xmm0
364 ; X64-LABEL: pinsrd_from_shufflevector_i32:
365 ; X64: ## BB#0: ## %entry
366 ; X64-NEXT: insertps $48, (%rdi), %xmm0
369 %0 = load <4 x i32>* %pb, align 16
370 %vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
371 ret <4 x i32> %vecinit6
374 define <4 x i32> @insertps_from_shufflevector_i32_2(<4 x i32> %a, <4 x i32> %b) {
375 ; X32-LABEL: insertps_from_shufflevector_i32_2:
376 ; X32: ## BB#0: ## %entry
377 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[3],xmm0[2,3]
380 ; X64-LABEL: insertps_from_shufflevector_i32_2:
381 ; X64: ## BB#0: ## %entry
382 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[3],xmm0[2,3]
385 %vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
386 ret <4 x i32> %vecinit6
389 define <4 x float> @insertps_from_load_ins_elt_undef(<4 x float> %a, float* %b) {
390 ; X32-LABEL: insertps_from_load_ins_elt_undef:
392 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
393 ; X32-NEXT: insertps $16, (%eax), %xmm0
396 ; X64-LABEL: insertps_from_load_ins_elt_undef:
398 ; X64-NEXT: insertps $16, (%rdi), %xmm0
400 %1 = load float* %b, align 4
401 %2 = insertelement <4 x float> undef, float %1, i32 0
402 %result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
403 ret <4 x float> %result
406 ; TODO: Like on pinsrd_from_shufflevector_i32, remove this mov instr
407 define <4 x i32> @insertps_from_load_ins_elt_undef_i32(<4 x i32> %a, i32* %b) {
408 ; X32-LABEL: insertps_from_load_ins_elt_undef_i32:
410 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
411 ; X32-NEXT: movd (%eax), %xmm1
412 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
415 ; X64-LABEL: insertps_from_load_ins_elt_undef_i32:
417 ; X64-NEXT: movd (%rdi), %xmm1
418 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
420 %1 = load i32* %b, align 4
421 %2 = insertelement <4 x i32> undef, i32 %1, i32 0
422 %result = shufflevector <4 x i32> %a, <4 x i32> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
423 ret <4 x i32> %result
426 ;;;;;; Shuffles optimizable with a single insertps instruction
427 define <4 x float> @shuf_XYZ0(<4 x float> %x, <4 x float> %a) {
428 ; X32-LABEL: shuf_XYZ0:
430 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
433 ; X64-LABEL: shuf_XYZ0:
435 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
437 %vecext = extractelement <4 x float> %x, i32 0
438 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
439 %vecext1 = extractelement <4 x float> %x, i32 1
440 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
441 %vecext3 = extractelement <4 x float> %x, i32 2
442 %vecinit4 = insertelement <4 x float> %vecinit2, float %vecext3, i32 2
443 %vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
444 ret <4 x float> %vecinit5
447 define <4 x float> @shuf_XY00(<4 x float> %x, <4 x float> %a) {
448 ; X32-LABEL: shuf_XY00:
450 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
453 ; X64-LABEL: shuf_XY00:
455 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
457 %vecext = extractelement <4 x float> %x, i32 0
458 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
459 %vecext1 = extractelement <4 x float> %x, i32 1
460 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
461 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.0, i32 2
462 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.0, i32 3
463 ret <4 x float> %vecinit4
466 define <4 x float> @shuf_XYY0(<4 x float> %x, <4 x float> %a) {
467 ; X32-LABEL: shuf_XYY0:
469 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
472 ; X64-LABEL: shuf_XYY0:
474 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
476 %vecext = extractelement <4 x float> %x, i32 0
477 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
478 %vecext1 = extractelement <4 x float> %x, i32 1
479 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
480 %vecinit4 = insertelement <4 x float> %vecinit2, float %vecext1, i32 2
481 %vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
482 ret <4 x float> %vecinit5
485 define <4 x float> @shuf_XYW0(<4 x float> %x, <4 x float> %a) {
486 ; X32-LABEL: shuf_XYW0:
488 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
491 ; X64-LABEL: shuf_XYW0:
493 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
495 %vecext = extractelement <4 x float> %x, i32 0
496 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
497 %vecext1 = extractelement <4 x float> %x, i32 1
498 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
499 %vecext2 = extractelement <4 x float> %x, i32 3
500 %vecinit3 = insertelement <4 x float> %vecinit2, float %vecext2, i32 2
501 %vecinit4 = insertelement <4 x float> %vecinit3, float 0.0, i32 3
502 ret <4 x float> %vecinit4
505 define <4 x float> @shuf_W00W(<4 x float> %x, <4 x float> %a) {
506 ; X32-LABEL: shuf_W00W:
508 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
511 ; X64-LABEL: shuf_W00W:
513 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
515 %vecext = extractelement <4 x float> %x, i32 3
516 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
517 %vecinit2 = insertelement <4 x float> %vecinit, float 0.0, i32 1
518 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.0, i32 2
519 %vecinit4 = insertelement <4 x float> %vecinit3, float %vecext, i32 3
520 ret <4 x float> %vecinit4
523 define <4 x float> @shuf_X00A(<4 x float> %x, <4 x float> %a) {
524 ; X32-LABEL: shuf_X00A:
526 ; X32-NEXT: xorps %xmm2, %xmm2
527 ; X32-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
528 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],zero,zero,xmm1[0]
529 ; X32-NEXT: movaps %xmm2, %xmm0
532 ; X64-LABEL: shuf_X00A:
534 ; X64-NEXT: xorps %xmm2, %xmm2
535 ; X64-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
536 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],zero,zero,xmm1[0]
537 ; X64-NEXT: movaps %xmm2, %xmm0
539 %vecext = extractelement <4 x float> %x, i32 0
540 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
541 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
542 %vecinit2 = insertelement <4 x float> %vecinit1, float 0.0, i32 2
543 %vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
544 ret <4 x float> %vecinit4
547 define <4 x float> @shuf_X00X(<4 x float> %x, <4 x float> %a) {
548 ; X32-LABEL: shuf_X00X:
550 ; X32-NEXT: xorps %xmm1, %xmm1
551 ; X32-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
552 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],zero,zero,xmm0[0]
553 ; X32-NEXT: movaps %xmm1, %xmm0
556 ; X64-LABEL: shuf_X00X:
558 ; X64-NEXT: xorps %xmm1, %xmm1
559 ; X64-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
560 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],zero,zero,xmm0[0]
561 ; X64-NEXT: movaps %xmm1, %xmm0
563 %vecext = extractelement <4 x float> %x, i32 0
564 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
565 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
566 %vecinit2 = insertelement <4 x float> %vecinit1, float 0.0, i32 2
567 %vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
568 ret <4 x float> %vecinit4
571 define <4 x float> @shuf_X0YC(<4 x float> %x, <4 x float> %a) {
572 ; X32-LABEL: shuf_X0YC:
574 ; X32-NEXT: xorps %xmm2, %xmm2
575 ; X32-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
576 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],zero,xmm0[1],zero
577 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
578 ; X32-NEXT: movaps %xmm2, %xmm0
581 ; X64-LABEL: shuf_X0YC:
583 ; X64-NEXT: xorps %xmm2, %xmm2
584 ; X64-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
585 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],zero,xmm0[1],zero
586 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
587 ; X64-NEXT: movaps %xmm2, %xmm0
589 %vecext = extractelement <4 x float> %x, i32 0
590 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
591 %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
592 %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 5, i32 undef>
593 %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
594 ret <4 x float> %vecinit5
597 define <4 x i32> @i32_shuf_XYZ0(<4 x i32> %x, <4 x i32> %a) {
598 ; X32-LABEL: i32_shuf_XYZ0:
600 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
603 ; X64-LABEL: i32_shuf_XYZ0:
605 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
607 %vecext = extractelement <4 x i32> %x, i32 0
608 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
609 %vecext1 = extractelement <4 x i32> %x, i32 1
610 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
611 %vecext3 = extractelement <4 x i32> %x, i32 2
612 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
613 %vecinit5 = insertelement <4 x i32> %vecinit4, i32 0, i32 3
614 ret <4 x i32> %vecinit5
617 define <4 x i32> @i32_shuf_XY00(<4 x i32> %x, <4 x i32> %a) {
618 ; X32-LABEL: i32_shuf_XY00:
620 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
623 ; X64-LABEL: i32_shuf_XY00:
625 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
627 %vecext = extractelement <4 x i32> %x, i32 0
628 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
629 %vecext1 = extractelement <4 x i32> %x, i32 1
630 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
631 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 0, i32 2
632 %vecinit4 = insertelement <4 x i32> %vecinit3, i32 0, i32 3
633 ret <4 x i32> %vecinit4
636 define <4 x i32> @i32_shuf_XYY0(<4 x i32> %x, <4 x i32> %a) {
637 ; X32-LABEL: i32_shuf_XYY0:
639 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
642 ; X64-LABEL: i32_shuf_XYY0:
644 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
646 %vecext = extractelement <4 x i32> %x, i32 0
647 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
648 %vecext1 = extractelement <4 x i32> %x, i32 1
649 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
650 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext1, i32 2
651 %vecinit5 = insertelement <4 x i32> %vecinit4, i32 0, i32 3
652 ret <4 x i32> %vecinit5
655 define <4 x i32> @i32_shuf_XYW0(<4 x i32> %x, <4 x i32> %a) {
656 ; X32-LABEL: i32_shuf_XYW0:
658 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
661 ; X64-LABEL: i32_shuf_XYW0:
663 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
665 %vecext = extractelement <4 x i32> %x, i32 0
666 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
667 %vecext1 = extractelement <4 x i32> %x, i32 1
668 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
669 %vecext2 = extractelement <4 x i32> %x, i32 3
670 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %vecext2, i32 2
671 %vecinit4 = insertelement <4 x i32> %vecinit3, i32 0, i32 3
672 ret <4 x i32> %vecinit4
675 define <4 x i32> @i32_shuf_W00W(<4 x i32> %x, <4 x i32> %a) {
676 ; X32-LABEL: i32_shuf_W00W:
678 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
681 ; X64-LABEL: i32_shuf_W00W:
683 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
685 %vecext = extractelement <4 x i32> %x, i32 3
686 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
687 %vecinit2 = insertelement <4 x i32> %vecinit, i32 0, i32 1
688 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 0, i32 2
689 %vecinit4 = insertelement <4 x i32> %vecinit3, i32 %vecext, i32 3
690 ret <4 x i32> %vecinit4
693 define <4 x i32> @i32_shuf_X00A(<4 x i32> %x, <4 x i32> %a) {
694 ; X32-LABEL: i32_shuf_X00A:
696 ; X32-NEXT: xorps %xmm2, %xmm2
697 ; X32-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
698 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[0]
699 ; X32-NEXT: movaps %xmm2, %xmm0
702 ; X64-LABEL: i32_shuf_X00A:
704 ; X64-NEXT: xorps %xmm2, %xmm2
705 ; X64-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
706 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[0]
707 ; X64-NEXT: movaps %xmm2, %xmm0
709 %vecext = extractelement <4 x i32> %x, i32 0
710 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
711 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
712 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
713 %vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
714 ret <4 x i32> %vecinit4
717 define <4 x i32> @i32_shuf_X00X(<4 x i32> %x, <4 x i32> %a) {
718 ; X32-LABEL: i32_shuf_X00X:
720 ; X32-NEXT: xorps %xmm1, %xmm1
721 ; X32-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
722 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
723 ; X32-NEXT: movaps %xmm1, %xmm0
726 ; X64-LABEL: i32_shuf_X00X:
728 ; X64-NEXT: xorps %xmm1, %xmm1
729 ; X64-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
730 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
731 ; X64-NEXT: movaps %xmm1, %xmm0
733 %vecext = extractelement <4 x i32> %x, i32 0
734 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
735 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
736 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
737 %vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
738 ret <4 x i32> %vecinit4
741 define <4 x i32> @i32_shuf_X0YC(<4 x i32> %x, <4 x i32> %a) {
742 ; X32-LABEL: i32_shuf_X0YC:
744 ; X32-NEXT: xorps %xmm2, %xmm2
745 ; X32-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
746 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1],zero
747 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
748 ; X32-NEXT: movaps %xmm2, %xmm0
751 ; X64-LABEL: i32_shuf_X0YC:
753 ; X64-NEXT: xorps %xmm2, %xmm2
754 ; X64-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
755 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1],zero
756 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
757 ; X64-NEXT: movaps %xmm2, %xmm0
759 %vecext = extractelement <4 x i32> %x, i32 0
760 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
761 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
762 %vecinit3 = shufflevector <4 x i32> %vecinit1, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 5, i32 undef>
763 %vecinit5 = shufflevector <4 x i32> %vecinit3, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
764 ret <4 x i32> %vecinit5
767 ;; Test for a bug in the first implementation of LowerBuildVectorv4x32
768 define < 4 x float> @test_insertps_no_undef(<4 x float> %x) {
769 ; X32-LABEL: test_insertps_no_undef:
771 ; X32-NEXT: movaps %xmm0, %xmm1
772 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],zero
773 ; X32-NEXT: maxps %xmm1, %xmm0
776 ; X64-LABEL: test_insertps_no_undef:
778 ; X64-NEXT: movaps %xmm0, %xmm1
779 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],zero
780 ; X64-NEXT: maxps %xmm1, %xmm0
782 %vecext = extractelement <4 x float> %x, i32 0
783 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
784 %vecext1 = extractelement <4 x float> %x, i32 1
785 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
786 %vecext3 = extractelement <4 x float> %x, i32 2
787 %vecinit4 = insertelement <4 x float> %vecinit2, float %vecext3, i32 2
788 %vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
789 %mask = fcmp olt <4 x float> %vecinit5, %x
790 %res = select <4 x i1> %mask, <4 x float> %x, <4 x float>%vecinit5
794 define <8 x i16> @blendvb_fallback(<8 x i1> %mask, <8 x i16> %x, <8 x i16> %y) {
795 ; X32-LABEL: blendvb_fallback:
797 ; X32-NEXT: psllw $15, %xmm0
798 ; X32-NEXT: psraw $15, %xmm0
799 ; X32-NEXT: pblendvb %xmm1, %xmm2
800 ; X32-NEXT: movdqa %xmm2, %xmm0
803 ; X64-LABEL: blendvb_fallback:
805 ; X64-NEXT: psllw $15, %xmm0
806 ; X64-NEXT: psraw $15, %xmm0
807 ; X64-NEXT: pblendvb %xmm1, %xmm2
808 ; X64-NEXT: movdqa %xmm2, %xmm0
810 %ret = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %y
814 ; On X32, account for the argument's move to registers
815 define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
816 ; X32-LABEL: insertps_from_vector_load:
818 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
819 ; X32-NEXT: insertps $48, (%eax), %xmm0
822 ; X64-LABEL: insertps_from_vector_load:
824 ; X64-NEXT: insertps $48, (%rdi), %xmm0
826 %1 = load <4 x float>* %pb, align 16
827 %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 48)
831 ;; Use a non-zero CountS for insertps
832 ;; Try to match a bit more of the instr, since we need the load's offset.
833 define <4 x float> @insertps_from_vector_load_offset(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
834 ; X32-LABEL: insertps_from_vector_load_offset:
836 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
837 ; X32-NEXT: insertps $96, 4(%eax), %xmm0
840 ; X64-LABEL: insertps_from_vector_load_offset:
842 ; X64-NEXT: insertps $96, 4(%rdi), %xmm0
844 %1 = load <4 x float>* %pb, align 16
845 %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
849 ;; Try to match a bit more of the instr, since we need the load's offset.
850 define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x float>* nocapture readonly %pb, i64 %index) {
851 ; X32-LABEL: insertps_from_vector_load_offset_2:
853 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
854 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
855 ; X32-NEXT: shll $4, %ecx
856 ; X32-NEXT: insertps $-64, 12(%eax,%ecx), %xmm0
859 ; X64-LABEL: insertps_from_vector_load_offset_2:
861 ; X64-NEXT: shlq $4, %rsi
862 ; X64-NEXT: insertps $-64, 12(%rdi,%rsi), %xmm0
864 %1 = getelementptr inbounds <4 x float>* %pb, i64 %index
865 %2 = load <4 x float>* %1, align 16
866 %3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
870 define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocapture readonly %fb, i64 %index) {
871 ; X32-LABEL: insertps_from_broadcast_loadf32:
873 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
874 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
875 ; X32-NEXT: movss (%ecx,%eax,4), %xmm1
876 ; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
877 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
880 ; X64-LABEL: insertps_from_broadcast_loadf32:
882 ; X64-NEXT: movss (%rdi,%rsi,4), %xmm1
883 ; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
884 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
886 %1 = getelementptr inbounds float* %fb, i64 %index
887 %2 = load float* %1, align 4
888 %3 = insertelement <4 x float> undef, float %2, i32 0
889 %4 = insertelement <4 x float> %3, float %2, i32 1
890 %5 = insertelement <4 x float> %4, float %2, i32 2
891 %6 = insertelement <4 x float> %5, float %2, i32 3
892 %7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
896 define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float>* nocapture readonly %b) {
897 ; X32-LABEL: insertps_from_broadcast_loadv4f32:
899 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
900 ; X32-NEXT: movups (%eax), %xmm1
901 ; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
902 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
905 ; X64-LABEL: insertps_from_broadcast_loadv4f32:
907 ; X64-NEXT: movups (%rdi), %xmm1
908 ; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
909 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
911 %1 = load <4 x float>* %b, align 4
912 %2 = extractelement <4 x float> %1, i32 0
913 %3 = insertelement <4 x float> undef, float %2, i32 0
914 %4 = insertelement <4 x float> %3, float %2, i32 1
915 %5 = insertelement <4 x float> %4, float %2, i32 2
916 %6 = insertelement <4 x float> %5, float %2, i32 3
917 %7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
921 ;; FIXME: We're emitting an extraneous pshufd/vbroadcast.
922 define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* nocapture readonly %fb, i64 %index) {
923 ; X32-LABEL: insertps_from_broadcast_multiple_use:
925 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
926 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
927 ; X32-NEXT: movss (%ecx,%eax,4), %xmm4
928 ; X32-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,0,0,0]
929 ; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
930 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
931 ; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm4[0]
932 ; X32-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
933 ; X32-NEXT: addps %xmm1, %xmm0
934 ; X32-NEXT: addps %xmm2, %xmm3
935 ; X32-NEXT: addps %xmm3, %xmm0
938 ; X64-LABEL: insertps_from_broadcast_multiple_use:
940 ; X64-NEXT: movss (%rdi,%rsi,4), %xmm4
941 ; X64-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,0,0,0]
942 ; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
943 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
944 ; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm4[0]
945 ; X64-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
946 ; X64-NEXT: addps %xmm1, %xmm0
947 ; X64-NEXT: addps %xmm2, %xmm3
948 ; X64-NEXT: addps %xmm3, %xmm0
950 %1 = getelementptr inbounds float* %fb, i64 %index
951 %2 = load float* %1, align 4
952 %3 = insertelement <4 x float> undef, float %2, i32 0
953 %4 = insertelement <4 x float> %3, float %2, i32 1
954 %5 = insertelement <4 x float> %4, float %2, i32 2
955 %6 = insertelement <4 x float> %5, float %2, i32 3
956 %7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
957 %8 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %b, <4 x float> %6, i32 48)
958 %9 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %c, <4 x float> %6, i32 48)
959 %10 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %d, <4 x float> %6, i32 48)
960 %11 = fadd <4 x float> %7, %8
961 %12 = fadd <4 x float> %9, %10
962 %13 = fadd <4 x float> %11, %12
966 define <4 x float> @insertps_with_undefs(<4 x float> %a, float* %b) {
967 ; X32-LABEL: insertps_with_undefs:
969 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
970 ; X32-NEXT: movss (%eax), %xmm1
971 ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],zero,xmm0[0],xmm1[3]
972 ; X32-NEXT: movaps %xmm1, %xmm0
975 ; X64-LABEL: insertps_with_undefs:
977 ; X64-NEXT: movss (%rdi), %xmm1
978 ; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],zero,xmm0[0],xmm1[3]
979 ; X64-NEXT: movaps %xmm1, %xmm0
981 %1 = load float* %b, align 4
982 %2 = insertelement <4 x float> undef, float %1, i32 0
983 %result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 4, i32 undef, i32 0, i32 7>
984 ret <4 x float> %result
987 ; Test for a bug in X86ISelLowering.cpp:getINSERTPS where we were using
988 ; the destination index to change the load, instead of the source index.
989 define <4 x float> @pr20087(<4 x float> %a, <4 x float> *%ptr) {
990 ; X32-LABEL: pr20087:
992 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
993 ; X32-NEXT: insertps $-78, 8(%eax), %xmm0
996 ; X64-LABEL: pr20087:
998 ; X64-NEXT: insertps $-78, 8(%rdi), %xmm0
1000 %load = load <4 x float> *%ptr
1001 %ret = shufflevector <4 x float> %load, <4 x float> %a, <4 x i32> <i32 4, i32 undef, i32 6, i32 2>
1002 ret <4 x float> %ret
1005 ; Edge case for insertps where we end up with a shuffle with mask=<0, 7, -1, -1>
1006 define void @insertps_pr20411(i32* noalias nocapture %RET) #1 {
1007 ; X32-LABEL: insertps_pr20411:
1009 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1010 ; X32-NEXT: pshufd {{.*#+}} xmm0 = mem[3,1,2,3]
1011 ; X32-NEXT: insertps $-36, LCPI49_1+12, %xmm0
1012 ; X32-NEXT: movups %xmm0, (%eax)
1015 ; X64-LABEL: insertps_pr20411:
1017 ; X64-NEXT: pshufd {{.*#+}} xmm0 = mem[3,1,2,3]
1018 ; X64-NEXT: insertps $-36, LCPI49_1+{{.*}}(%rip), %xmm0
1019 ; X64-NEXT: movups %xmm0, (%rdi)
1021 %gather_load = shufflevector <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1022 %shuffle109 = shufflevector <4 x i32> <i32 4, i32 5, i32 6, i32 7>, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; 4 5 6 7
1023 %shuffle116 = shufflevector <8 x i32> %gather_load, <8 x i32> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; 3 x x x
1024 %shuffle117 = shufflevector <4 x i32> %shuffle109, <4 x i32> %shuffle116, <4 x i32> <i32 4, i32 3, i32 undef, i32 undef> ; 3 7 x x
1025 %ptrcast = bitcast i32* %RET to <4 x i32>*
1026 store <4 x i32> %shuffle117, <4 x i32>* %ptrcast, align 4