1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim | FileCheck %s
3 ; Note: Print verbose stackmaps using -debug-only=stackmaps.
5 ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
6 ; CHECK-NEXT: __LLVM_StackMaps:
10 ; CHECK-NEXT: .quad 4294967296
12 ; CHECK-NEXT: .long 14
17 ; CHECK-NEXT: .long L{{.*}}-_constantargs
18 ; CHECK-NEXT: .short 0
19 ; CHECK-NEXT: .short 4
23 ; CHECK-NEXT: .short 0
24 ; CHECK-NEXT: .long 65535
28 ; CHECK-NEXT: .short 0
29 ; CHECK-NEXT: .long 65536
33 ; CHECK-NEXT: .short 0
34 ; CHECK-NEXT: .long -1
35 ; LargeConstant at index 0
38 ; CHECK-NEXT: .short 0
41 define void @constantargs() {
43 %0 = inttoptr i64 12345 to i8*
44 tail call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 1, i32 15, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
51 ; CHECK-NEXT: .long L{{.*}}-_osrinline
52 ; CHECK-NEXT: .short 0
53 ; CHECK-NEXT: .short 2
56 ; CHECK-NEXT: .short {{[0-9]+}}
60 ; CHECK-NEXT: .short {{[0-9]+}}
62 define void @osrinline(i64 %a, i64 %b) {
64 ; Runtime void->void call.
65 call void inttoptr (i64 -559038737 to void ()*)()
66 ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
67 call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 3, i32 12, i64 %a, i64 %b)
73 ; 2 live variables in register.
76 ; CHECK-NEXT: .long L{{.*}}-_osrcold
77 ; CHECK-NEXT: .short 0
78 ; CHECK-NEXT: .short 2
81 ; CHECK-NEXT: .short {{[0-9]+}}
85 ; CHECK-NEXT: .short {{[0-9]+}}
87 define void @osrcold(i64 %a, i64 %b) {
89 %test = icmp slt i64 %a, %b
90 br i1 %test, label %ret, label %cold
92 ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
93 %thunk = inttoptr i64 -559038737 to i8*
94 call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 4, i32 15, i8* %thunk, i32 0, i64 %a, i64 %b)
101 ; CHECK-NEXT: .long 5
102 ; CHECK-NEXT: .long L{{.*}}-_propertyRead
103 ; CHECK-NEXT: .short 0
104 ; CHECK-NEXT: .short 2
105 ; CHECK-NEXT: .byte 1
106 ; CHECK-NEXT: .byte 8
107 ; CHECK-NEXT: .short {{[0-9]+}}
108 ; CHECK-NEXT: .long 0
109 ; CHECK-NEXT: .byte 1
110 ; CHECK-NEXT: .byte 8
111 ; CHECK-NEXT: .short {{[0-9]+}}
112 ; CHECK-NEXT: .long 0
113 define i64 @propertyRead(i64* %obj) {
115 %resolveRead = inttoptr i64 -559038737 to i8*
116 %result = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 5, i32 15, i8* %resolveRead, i32 1, i64* %obj)
117 %add = add i64 %result, 3
122 ; CHECK-NEXT: .long 6
123 ; CHECK-NEXT: .long L{{.*}}-_propertyWrite
124 ; CHECK-NEXT: .short 0
125 ; CHECK-NEXT: .short 2
126 ; CHECK-NEXT: .byte 1
127 ; CHECK-NEXT: .byte 8
128 ; CHECK-NEXT: .short {{[0-9]+}}
129 ; CHECK-NEXT: .long 0
130 ; CHECK-NEXT: .byte 1
131 ; CHECK-NEXT: .byte 8
132 ; CHECK-NEXT: .short {{[0-9]+}}
133 ; CHECK-NEXT: .long 0
134 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
136 %resolveWrite = inttoptr i64 -559038737 to i8*
137 call anyregcc void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 6, i32 15, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
143 ; 2 live variables in registers.
145 ; CHECK-NEXT: .long 7
146 ; CHECK-NEXT: .long L{{.*}}-_jsVoidCall
147 ; CHECK-NEXT: .short 0
148 ; CHECK-NEXT: .short 2
149 ; CHECK-NEXT: .byte 1
150 ; CHECK-NEXT: .byte 8
151 ; CHECK-NEXT: .short {{[0-9]+}}
152 ; CHECK-NEXT: .long 0
153 ; CHECK-NEXT: .byte 1
154 ; CHECK-NEXT: .byte 8
155 ; CHECK-NEXT: .short {{[0-9]+}}
156 ; CHECK-NEXT: .long 0
157 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
159 %resolveCall = inttoptr i64 -559038737 to i8*
160 call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 7, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
166 ; 2 live variables in registers.
169 ; CHECK-NEXT: .long L{{.*}}-_jsIntCall
170 ; CHECK-NEXT: .short 0
171 ; CHECK-NEXT: .short 2
172 ; CHECK-NEXT: .byte 1
173 ; CHECK-NEXT: .byte 8
174 ; CHECK-NEXT: .short {{[0-9]+}}
175 ; CHECK-NEXT: .long 0
176 ; CHECK-NEXT: .byte 1
177 ; CHECK-NEXT: .byte 8
178 ; CHECK-NEXT: .short {{[0-9]+}}
179 ; CHECK-NEXT: .long 0
180 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
182 %resolveCall = inttoptr i64 -559038737 to i8*
183 %result = call i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 8, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
184 %add = add i64 %result, 3
188 ; Spilled stack map values.
190 ; Verify 17 stack map entries.
193 ; CHECK-NEXT: .long L{{.*}}-_spilledValue
194 ; CHECK-NEXT: .short 0
195 ; CHECK-NEXT: .short 17
197 ; Check that at least one is a spilled entry from RBP.
198 ; Location: Indirect RBP + ...
200 ; CHECK-NEXT: .byte 8
201 ; CHECK-NEXT: .short 6
202 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
204 call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 11, i32 15, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
208 ; Spilled stack map values.
210 ; Verify 17 stack map entries.
213 ; CHECK-LABEL: .long L{{.*}}-_spilledStackMapValue
214 ; CHECK-NEXT: .short 0
215 ; CHECK-NEXT: .short 17
217 ; Check that at least one is a spilled entry from RBP.
218 ; Location: Indirect RBP + ...
220 ; CHECK-NEXT: .byte 8
221 ; CHECK-NEXT: .short 6
222 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
224 call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 12, i32 15, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
228 ; Spill a subregister stackmap operand.
231 ; CHECK-LABEL: .long L{{.*}}-_spillSubReg
232 ; CHECK-NEXT: .short 0
234 ; CHECK-NEXT: .short 1
236 ; Check that the subregister operand is a 4-byte spill.
237 ; Location: Indirect, 4-byte, RBP + ...
239 ; CHECK-NEXT: .byte 4
240 ; CHECK-NEXT: .short 6
241 define void @spillSubReg(i64 %arg) #0 {
243 br i1 undef, label %bb1, label %bb2
249 %tmp = load i64* inttoptr (i64 140685446136880 to i64*)
250 br i1 undef, label %bb16, label %bb17
256 %tmp32 = trunc i64 %tmp to i32
257 br i1 undef, label %bb60, label %bb61
260 tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
261 tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 13, i32 5, i32 %tmp32)
268 ; Map a single byte subregister. There is no DWARF register number, so
269 ; we expect the register to be encoded with the proper size and spill offset. We don't know which
272 ; CHECK-LABEL: .long L{{.*}}-_subRegOffset
273 ; CHECK-NEXT: .short 0
275 ; CHECK-NEXT: .short 2
277 ; Check that the subregister operands are 1-byte spills.
278 ; Location 0: Register, 4-byte, AL
279 ; CHECK-NEXT: .byte 1
280 ; CHECK-NEXT: .byte 1
281 ; CHECK-NEXT: .short 0
282 ; CHECK-NEXT: .long 0
284 ; Location 1: Register, 4-byte, BL
285 ; CHECK-NEXT: .byte 1
286 ; CHECK-NEXT: .byte 1
287 ; CHECK-NEXT: .short 3
288 ; CHECK-NEXT: .long 0
289 define void @subRegOffset(i16 %arg) {
291 %a0 = trunc i16 %v to i8
292 tail call void asm sideeffect "nop", "~{bx}"() nounwind
293 %arghi = lshr i16 %v, 8
294 %a1 = trunc i16 %arghi to i8
295 tail call void asm sideeffect "nop", "~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
296 tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 14, i32 5, i8 %a0, i8 %a1)
300 ; Map a constant value.
303 ; CHECK-LABEL: .long L{{.*}}-_liveConstant
304 ; CHECK-NEXT: .short 0
306 ; CHECK-NEXT: .short 1
307 ; Loc 0: SmallConstant
308 ; CHECK-NEXT: .byte 4
309 ; CHECK-NEXT: .byte 8
310 ; CHECK-NEXT: .short 0
311 ; CHECK-NEXT: .long 33
313 define void @liveConstant() {
314 tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 15, i32 5, i32 33)
318 ; Directly map an alloca's address.
322 ; CHECK-LABEL: .long L{{.*}}-_directFrameIdx
323 ; CHECK-NEXT: .short 0
325 ; CHECK-NEXT: .short 1
326 ; Loc 0: Direct RBP - ofs
327 ; CHECK-NEXT: .byte 2
328 ; CHECK-NEXT: .byte 8
329 ; CHECK-NEXT: .short 6
332 ; CHECK-NEXT: .long 17
333 ; CHECK-NEXT: .long L{{.*}}-_directFrameIdx
334 ; CHECK-NEXT: .short 0
336 ; CHECK-NEXT: .short 2
337 ; Loc 0: Direct RBP - ofs
338 ; CHECK-NEXT: .byte 2
339 ; CHECK-NEXT: .byte 8
340 ; CHECK-NEXT: .short 6
342 ; Loc 1: Direct RBP - ofs
343 ; CHECK-NEXT: .byte 2
344 ; CHECK-NEXT: .byte 8
345 ; CHECK-NEXT: .short 6
347 define void @directFrameIdx() {
349 %metadata1 = alloca i64, i32 3, align 8
350 store i64 11, i64* %metadata1
351 store i64 12, i64* %metadata1
352 store i64 13, i64* %metadata1
353 call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 16, i32 0, i64* %metadata1)
354 %metadata2 = alloca i8, i32 4, align 8
355 %metadata3 = alloca i16, i32 4, align 8
356 call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 17, i32 5, i8* null, i32 0, i8* %metadata2, i16* %metadata3)
360 declare void @llvm.experimental.stackmap(i32, i32, ...)
361 declare void @llvm.experimental.patchpoint.void(i32, i32, i8*, i32, ...)
362 declare i64 @llvm.experimental.patchpoint.i64(i32, i32, i8*, i32, ...)