1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim | FileCheck %s
3 ; Note: Print verbose stackmaps using -debug-only=stackmaps.
5 ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
6 ; CHECK-NEXT: __LLVM_StackMaps:
10 ; CHECK-NEXT: .quad 4294967296
12 ; CHECK-NEXT: .long 14
17 ; CHECK-NEXT: .long L{{.*}}-_constantargs
18 ; CHECK-NEXT: .short 0
19 ; CHECK-NEXT: .short 4
23 ; CHECK-NEXT: .short 0
24 ; CHECK-NEXT: .long 65535
28 ; CHECK-NEXT: .short 0
29 ; CHECK-NEXT: .long 65536
33 ; CHECK-NEXT: .short 0
34 ; CHECK-NEXT: .long -1
35 ; LargeConstant at index 0
38 ; CHECK-NEXT: .short 0
41 define void @constantargs() {
43 %0 = inttoptr i64 12345 to i8*
44 tail call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 1, i32 15, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
51 ; CHECK-NEXT: .long L{{.*}}-_osrinline
52 ; CHECK-NEXT: .short 0
53 ; CHECK-NEXT: .short 2
56 ; CHECK-NEXT: .short {{[0-9]+}}
60 ; CHECK-NEXT: .short {{[0-9]+}}
62 define void @osrinline(i64 %a, i64 %b) {
64 ; Runtime void->void call.
65 call void inttoptr (i64 -559038737 to void ()*)()
66 ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
67 call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 3, i32 12, i64 %a, i64 %b)
73 ; 2 live variables in register.
76 ; CHECK-NEXT: .long L{{.*}}-_osrcold
77 ; CHECK-NEXT: .short 0
78 ; CHECK-NEXT: .short 2
81 ; CHECK-NEXT: .short {{[0-9]+}}
85 ; CHECK-NEXT: .short {{[0-9]+}}
87 define void @osrcold(i64 %a, i64 %b) {
89 %test = icmp slt i64 %a, %b
90 br i1 %test, label %ret, label %cold
92 ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
93 %thunk = inttoptr i64 -559038737 to i8*
94 call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 4, i32 15, i8* %thunk, i32 0, i64 %a, i64 %b)
101 ; CHECK-NEXT: .long 5
102 ; CHECK-NEXT: .long L{{.*}}-_propertyRead
103 ; CHECK-NEXT: .short 0
104 ; CHECK-NEXT: .short 0
106 ; FIXME: There are currently no stackmap entries. After moving to
107 ; AnyRegCC, we will have entries for the object and return value.
108 define i64 @propertyRead(i64* %obj) {
110 %resolveRead = inttoptr i64 -559038737 to i8*
111 %result = call i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 5, i32 15, i8* %resolveRead, i32 1, i64* %obj)
112 %add = add i64 %result, 3
117 ; CHECK-NEXT: .long 6
118 ; CHECK-NEXT: .long L{{.*}}-_propertyWrite
119 ; CHECK-NEXT: .short 0
120 ; CHECK-NEXT: .short 0
122 ; FIXME: There are currently no stackmap entries. After moving to
123 ; AnyRegCC, we will have entries for the object and return value.
124 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
126 %resolveWrite = inttoptr i64 -559038737 to i8*
127 call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 6, i32 15, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
133 ; 2 live variables in registers.
135 ; CHECK-NEXT: .long 7
136 ; CHECK-NEXT: .long L{{.*}}-_jsVoidCall
137 ; CHECK-NEXT: .short 0
138 ; CHECK-NEXT: .short 2
139 ; CHECK-NEXT: .byte 1
140 ; CHECK-NEXT: .byte 8
141 ; CHECK-NEXT: .short {{[0-9]+}}
142 ; CHECK-NEXT: .long 0
143 ; CHECK-NEXT: .byte 1
144 ; CHECK-NEXT: .byte 8
145 ; CHECK-NEXT: .short {{[0-9]+}}
146 ; CHECK-NEXT: .long 0
147 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
149 %resolveCall = inttoptr i64 -559038737 to i8*
150 call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 7, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
156 ; 2 live variables in registers.
159 ; CHECK-NEXT: .long L{{.*}}-_jsIntCall
160 ; CHECK-NEXT: .short 0
161 ; CHECK-NEXT: .short 2
162 ; CHECK-NEXT: .byte 1
163 ; CHECK-NEXT: .byte 8
164 ; CHECK-NEXT: .short {{[0-9]+}}
165 ; CHECK-NEXT: .long 0
166 ; CHECK-NEXT: .byte 1
167 ; CHECK-NEXT: .byte 8
168 ; CHECK-NEXT: .short {{[0-9]+}}
169 ; CHECK-NEXT: .long 0
170 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
172 %resolveCall = inttoptr i64 -559038737 to i8*
173 %result = call i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 8, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
174 %add = add i64 %result, 3
178 ; Spilled stack map values.
180 ; Verify 17 stack map entries.
183 ; CHECK-NEXT: .long L{{.*}}-_spilledValue
184 ; CHECK-NEXT: .short 0
185 ; CHECK-NEXT: .short 17
187 ; Check that at least one is a spilled entry from RBP.
188 ; Location: Indirect RBP + ...
190 ; CHECK-NEXT: .byte 8
191 ; CHECK-NEXT: .short 6
192 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
194 call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 11, i32 15, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
198 ; Spilled stack map values.
200 ; Verify 17 stack map entries.
203 ; CHECK-LABEL: .long L{{.*}}-_spilledStackMapValue
204 ; CHECK-NEXT: .short 0
205 ; CHECK-NEXT: .short 17
207 ; Check that at least one is a spilled entry from RBP.
208 ; Location: Indirect RBP + ...
210 ; CHECK-NEXT: .byte 8
211 ; CHECK-NEXT: .short 6
212 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
214 call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 12, i32 15, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
218 ; Spill a subregister stackmap operand.
221 ; CHECK-LABEL: .long L{{.*}}-_spillSubReg
222 ; CHECK-NEXT: .short 0
224 ; CHECK-NEXT: .short 1
226 ; Check that the subregister operand is a 4-byte spill.
227 ; Location: Indirect, 4-byte, RBP + ...
229 ; CHECK-NEXT: .byte 4
230 ; CHECK-NEXT: .short 6
231 define void @spillSubReg(i64 %arg) #0 {
233 br i1 undef, label %bb1, label %bb2
239 %tmp = load i64* inttoptr (i64 140685446136880 to i64*)
240 br i1 undef, label %bb16, label %bb17
246 %tmp32 = trunc i64 %tmp to i32
247 br i1 undef, label %bb60, label %bb61
250 tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
251 tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 13, i32 5, i32 %tmp32)
258 ; Map a single byte subregister. There is no DWARF register number, so
259 ; we expect the register to be encoded with the proper size and spill offset. We don't know which
262 ; CHECK-LABEL: .long L{{.*}}-_subRegOffset
263 ; CHECK-NEXT: .short 0
265 ; CHECK-NEXT: .short 2
267 ; Check that the subregister operands are 1-byte spills.
268 ; Location 0: Register, 4-byte, AL
269 ; CHECK-NEXT: .byte 1
270 ; CHECK-NEXT: .byte 1
271 ; CHECK-NEXT: .short 0
272 ; CHECK-NEXT: .long 0
274 ; Location 1: Register, 4-byte, BL
275 ; CHECK-NEXT: .byte 1
276 ; CHECK-NEXT: .byte 1
277 ; CHECK-NEXT: .short 3
278 ; CHECK-NEXT: .long 0
279 define void @subRegOffset(i16 %arg) {
281 %a0 = trunc i16 %v to i8
282 tail call void asm sideeffect "nop", "~{bx}"() nounwind
283 %arghi = lshr i16 %v, 8
284 %a1 = trunc i16 %arghi to i8
285 tail call void asm sideeffect "nop", "~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
286 tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 14, i32 5, i8 %a0, i8 %a1)
290 ; Map a constant value.
293 ; CHECK-LABEL: .long L{{.*}}-_liveConstant
294 ; CHECK-NEXT: .short 0
296 ; CHECK-NEXT: .short 1
297 ; Loc 0: SmallConstant
298 ; CHECK-NEXT: .byte 4
299 ; CHECK-NEXT: .byte 8
300 ; CHECK-NEXT: .short 0
301 ; CHECK-NEXT: .long 33
303 define void @liveConstant() {
304 tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 15, i32 5, i32 33)
308 ; Directly map an alloca's address.
312 ; CHECK-LABEL: .long L{{.*}}-_directFrameIdx
313 ; CHECK-NEXT: .short 0
315 ; CHECK-NEXT: .short 1
316 ; Loc 0: Direct RBP - ofs
317 ; CHECK-NEXT: .byte 2
318 ; CHECK-NEXT: .byte 8
319 ; CHECK-NEXT: .short 6
322 ; CHECK-NEXT: .long 17
323 ; CHECK-NEXT: .long L{{.*}}-_directFrameIdx
324 ; CHECK-NEXT: .short 0
326 ; CHECK-NEXT: .short 2
327 ; Loc 0: Direct RBP - ofs
328 ; CHECK-NEXT: .byte 2
329 ; CHECK-NEXT: .byte 8
330 ; CHECK-NEXT: .short 6
332 ; Loc 1: Direct RBP - ofs
333 ; CHECK-NEXT: .byte 2
334 ; CHECK-NEXT: .byte 8
335 ; CHECK-NEXT: .short 6
337 define void @directFrameIdx() {
339 %metadata1 = alloca i64, i32 3, align 8
340 store i64 11, i64* %metadata1
341 store i64 12, i64* %metadata1
342 store i64 13, i64* %metadata1
343 call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 16, i32 0, i64* %metadata1)
344 %metadata2 = alloca i8, i32 4, align 8
345 %metadata3 = alloca i16, i32 4, align 8
346 call void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 17, i32 5, i8* null, i32 0, i8* %metadata2, i16* %metadata3)
350 declare void @llvm.experimental.stackmap(i32, i32, ...)
351 declare void @llvm.experimental.patchpoint.void(i32, i32, i8*, i32, ...)
352 declare i64 @llvm.experimental.patchpoint.i64(i32, i32, i8*, i32, ...)